MVME5100 Single Board Computer Programmer's Reference Guide

I
N
D
E
X
C
cache
coherency restrictions 3-11
coherency SMC 3-11
support 2-25, 2-29
Cache Control Register 1-10
Cache Speed 1-10
CHRP memory 1-4
CHRP Memory Maps (suggested) 1-6
CLK FREQUENCY 3-44
CLK Frequency Register
SMC 3-44
clock frequency 3-44
combining, merging, and collapsing 2-28
command types 2-23
from PCI Master 2-27
PPC slave 2-8
CONADD and CONDAT Registers 1-19
CONFIG_ADDRESS Register 2-106
CONFIG_DATA Register 2-109
configuration
options on Hawk 3-35
registers 2-19
requirements on Hawk 3-35
type, as used by PHB 2-31
configurations
MVME21xx xxii
contention
between PCI and PPC 2-45
handling explained (PHB) 2-45
control bit
descriptions 3-38
core frequency 1-9
Critical Word First (CWF)
as supported by PCI Master 2-26
CSR
accesses to SMC 3-34
architecture of SMC 3-35
base address 3-35
reads and writes 3-35
Current Task Priority Register 2-127
CWF burst transfers
explained 2-26
cycle types
SMC 3-11
Index
D
data
discarded from prefetched reads 2-13
data parity
PPC 2-17
Data Parity Error Address Register
SMC 3-62
Data Parity Error Log Register
SMC 3-61
Data Parity Error Lower Data Register
SMC 3-63
Data Parity Error Upper Data Register
SMC 3-62
data throughput
PPC Slave to PCI Master 2-9
data transfer
PPC Master rates 2-10
relationship between PCI Slave and
PPC60x bus 2-11
data transfers
SMC 3-9
decoder
priorities 2-21
decoders
address PCI to PPC 2-6
for PCI to PPC addressing 2-20
PPC to PCI 2-7
delayed transactions
PCI Slave 2-24
derc 3-48
device selection 2-24
Disable Error Correction control bit 3-48
documentation, related B-1
DRAM
connection diagram 3-4
enable bits 3-41
size control bits 3-41
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