MVME5100 Single Board Computer Programmer's Reference Guide

2
Hawk PCI Host Bridge & Multi-Processor Interrupt Controller
While RST_ is asserted, XARB0 through XARB4 is held in tri-state. If the
internal arbiter mode is selected, then XARB0 through XARB3 is driven
to an active state no more than ten clock periods after PHB has detected a
rising edge on RST_. If the external arbiter mode has been selected, then
XARB4 is driven to an active state no more than ten clock periods after
PHB has detected a rising edge on RST_.
The PPC Arbiter implements the following prioritization scheme:
❏ HAWK (Highest Priority)
❏ EXTL
❏ CPUx
❏ CPUy (Lowest Priority)
The PPC Arbiter is controlled by the XARB register within the PHB
PPC60x register group.
The PPC Arbiter supports two prioritization schemes. Both schemes affect
the priority of the CPU’s with respect to each other. The CPU fixed option
always places the priority of CPU0 over CPU1. The CPU rotating option
gives priority on a rotational basis between CPU0 and CPU1. In all cases,
the priority of the CPUs remains fixed with respect to the priority of
HAWK and EXTL, with HAWK always having the highest priority of all.
The PPC Arbiter supports four parking modes. Parking is implemented
only on the CPUs and is not implemented on either HAWK or EXTL. The
parking options include parking on CPU0, parking on CPU1, parking on
the last CPU, or parking disabled.
There are various system level debug functions provided by the PPC
Arbiter. The PPC Arbiter has the optional ability to flatten the PPC60x bus
pipeline. Flattening can be imposed uniquely on single beat reads, single
beat writes, burst reads, and burst writes. It is possible to further qualify the
ability to flatten based on whether there is a switch in masters or whether
to flatten unconditionally for each transfer type. This is a debug function
only and is not intended for normal operation.
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