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ATLAS 550 System Manual - Adtran

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<strong>ATLAS</strong> <strong>550</strong> <strong>System</strong> <strong>Manual</strong> Section 4 User Interface Guide<br />

MODULES (V35NX-2) > PLL/FIFO > PORT<br />

Read security: 5<br />

Indicates the operating port. There are 2 available interfaces on the Dual Nx56/64 Option Module.<br />

MODULES (V35NX-2) > PLL/FIFO > PLL/FIFO<br />

Read security: 5<br />

Displays the state of the PLL and FIFO systems.<br />

LOCK PLL is locked (This is required to transfer data.)<br />

RXE Receive data FIFO empty.<br />

RXF Receive data FIFO full.<br />

TXE Transmit data FIFO empty.<br />

TXF Transmit data FIFO full.<br />

MODULES (V35NX-2) > CONFIGURATION<br />

Write security: 3; Read security: 5<br />

All of the following configurable parameters apply to the individual V.35 ports.<br />

MODULES (V35NX-2) > CONFIGURATION > PRT<br />

Read security: 5<br />

Displays the port number. There are 2 available interfaces on the Dual Nx56/64 Option Module.<br />

MODULES (V35NX-2) > CONFIGURATION > PORT NAME<br />

Write security: 3; Read security: 5<br />

Accepts any alpha-numeric name up to 17 characters long, to uniquely identify each port on the Dual<br />

Nx56/64 Option Module.<br />

MODULES (V35NX-2) > CONFIGURATION > CLK +/-<br />

Write security: 3; Read security: 5<br />

Controls the clock used by the <strong>ATLAS</strong> <strong>550</strong> to accept the transmit (TX) data from the DTE. This is usually<br />

set to NORMAL. If the interface cable is long, causing a phase shift in the data, the clock can be set to<br />

INVERTED. This switches the phase of the clock, which compensates for a long cable.<br />

MODULES (V35NX-2) > CONFIGURATION > DATA<br />

Write security: 3; Read security: 5<br />

Controls the inverting of the DTE data. This inversion can be useful when operating with a high-level data<br />

link control (HDLC) protocol (often used as a means to ensure 1s density). Select either NORMAL or<br />

INVERTED. Data inversion configuration must match at both ends of the circuit.<br />

61200305L2-1B © 2004 ADTRAN, Inc. 131

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