VisualDSP++ 4.5 Loader and Utilities Manual - Analog Devices

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ADSP-2106x/21160 Processor Booting 2. The boot kernel runs and loads the application executable code and data. 3. The boot kernel overwrites itself with the first 256 words of the application at the end of the booting process. After that, the application executable code begins to execute from locations 0x20000 (ADSP-21060/61/62), 0x8000 (ADSP-21065L), and 0x40000 (ADSP-21160). The start addresses and reset vector addresses are summarized in Table 3-2. Table 3-2. ADSP-2106x/21160 Processor Start Addresses Processor Start Address Reset Vector Address 1 ADSP-21060 0x20000 0x20004 ADSP-21061 0x20000 0x20004 ADSP-21062 0x20000 0x20004 ADSP-21065L 0x8000 0x8004 ADSP-21160 0x40000 0x40004 1 The reset vector address must not contain a valid instruction since it is not executed during the booting sequence. Place a NOP or IDLE instruction at this location. The boot type selection directs the system to prepare the appropriate boot kernel. 3-4 VisualDSP++ 4.5 Loader and Utilities Manual
Boot Mode Selection Loader for ADSP-2106x/21160 SHARC Processors The state of various pins selects the processor boot mode. For ADSP-21060, ADSP-21061, ADSP-21062, and ADSP-21160 processors, refer to Table 3-3 and Table 3-4. For ADSP-21065L processors, refer to Table 3-5 and Table 3-6. Table 3-3. ADSP-21060/061/062 and ADSP-21160 Boot Mode Pins Pin Type Description EBOOT I EPROM boot. When EBOOT is high, the processor boot-loads from an 8-bit EPROM through the processor’s external port. When EBOOT is low, the LBOOT and BMS pins determine the booting mode. LBOOT I Link port boot. When LBOOT is high and EBOOT is low, the processor boots from another SHARC through the link port. When LBOOT is low and EBOOT is low, the processor boots from a host processor through the processor’s external port. BMS I/O/T 1 Boot memory select. When boot-loading from an EPROM (EBOOT=1 and LBOOT=0), this pin is an output and serves as the chip select for the EPROM. In a multiprocessor system, BMS is output by the bus master. When host-booting or link-booting (EBOOT=0), BMS is an input and must be high. 1 Three-statable in EPROM boot mode (when BMS is an output). Table 3-4. ADSP-21060/061/062 and ADSP-21160 Boot Modes EBOOT LBOOT BMS Boot Mode 0 0 0 (Input) No-boot (processor executes from external memory) 0 0 1 (Input) Host processor 0 1 0 (Input) Reserved 0 1 1 (Input) Link port 1 0 Output EPROM (BMS is chip select) 1 1 x (Input) Reserved VisualDSP++ 4.5 Loader and Utilities Manual 3-5
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Analog Devices, Inc. One Technology
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CONTENTS PREFACE Purpose of This Ma
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CONTENTS Loader Files Without a Sec
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CONTENTS ADSP-BF535 and ADSP-BF531/
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Contents File Extensions ..........
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Contents Boot Type Selection ......
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PREFACE Thank you for purchasing Vi
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Technical or Customer Support Prefa
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ADSP-21367 ADSP-21368 ADSP21369 ADS
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Preface VisualDSP++ 4.5 C/C++ Compi
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VisualDSP++ Documentation Set Prefa
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1 INTRODUCTION The majority of this
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Loader Command Line Introduction If
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Initialization Code Introduction In
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A brief description of each phase f
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Introduction Download the loadable
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Introduction You can run the loader
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PROM Boot Mode Introduction After r
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Boot Streams Introduction The loade
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2 LOADER/SPLITTER FOR BLACKFIN PROC
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Loader/Splitter for Blackfin Proces
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System Reset Configuration Register
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D7 OUTPUT .LDR FILE 4-BYTE HEADER F
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Second-Stage Loader Restrictions Lo
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SPI Memory Detection Routine Loader
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Page 73 and 74: Loader/Splitter for Blackfin Proces
Page 77 and 78: P0.H = HI(EBIU_SDRRC); R0 = 0x074A(
Page 79 and 80: � Booting � SDRAM ADSP-BF536 pr
Page 85 and 86: 1-0-Byte Block Header Block Data Lo
Page 93 and 94: � The Core B Loader/Splitter for
Page 95 and 96: INITIALIZATION CODE (KERNEL WITH DE
Page 99 and 100: FLASH MEMORY INIT CODE HEADER INIT
Page 101 and 102: where: � Command-line File Search
Page 103 and 104: Blackfin Loader Command-Line Switch
Page 111 and 112: Using Base Loader Loader/Splitter f
Page 113 and 114: Table 2-11. Base Load Page Settings
Page 115 and 116: Using Second-Stage Loader Loader/Sp
Page 121 and 122: 3 LOADER FOR ADSP-2106X/21160 SHARC
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Page 127 and 128: Loader for ADSP-2106x/21160 SHARC P
Page 147 and 148: File Searches Loader for ADSP-2106x
Page 151 and 152: -si-revision #|none|any Loader for
Page 153 and 154: 4 LOADER FOR ADSP-21161 SHARC PROCE
Page 155 and 156: Loader for ADSP-21161 SHARC Process
Page 169 and 170: ADSP-21161 Processor Boot Streams L
Page 171 and 172: To Modify a Boot Kernel Source File
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Processor ID Numbers Loader for ADS
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Loader for ADSP-21161 SHARC Process
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File Searches Loader for ADSP-21161
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5 LOADER FOR ADSP-2126X/2136X/2137X
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Loader for ADSP-2126x/2136x/2137x S
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File Searches Loader for ADSP-2126x
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6 LOADER FOR TIGERSHARC PROCESSORS
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� EE-174: Loader for TigerSHARC P
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Boot Kernel Modification Loader for
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Loader for TigerSHARC Processors el
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TigerSHARC Command-Line Switches Lo
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Loader for TigerSHARC Processors Ta
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7 SPLITTER FOR SHARC AND TIGERSHARC
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� Most Splitter for SHARC and Tig
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Splitter for SHARC and TigerSHARC P
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A FILE FORMATS VisualDSP++ developm
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Assembly Source Files File Formats
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Build Files File Formats Build file
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Memory Map Files File Formats The l
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Table A-4. End-of-File Record Examp
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This example shows how to include t
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Table A-7. S1 Termination Record Ex
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File Formats A block of data record
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Table A-9. SPORT Data File Example
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B UTILITIES The VisualDSP++ develop
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elf2flt - ELF to BFLT File Converte
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Table B-3. BFLT File Dumper Command
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I INDEX Numerics -64 splitter switc
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BMS pins ADSP-2106x/160 processors,
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data initialization files (.dat), A
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external memory (SHARC processors)
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initialization blocks (Blackfin pro
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loader file formats (ADSP-BF535 pro
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P -p # loader switch for Blackfin,
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shared memory Blackfin processors,
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V .VAR directive, A-3 vector addres
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VisualDSP++ 4.5 Loader and Utilities Manual - Analog Devices

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