VisualDSP++ 4.5 Loader and Utilities Manual - Analog Devices

Blackfin Processor Booting
For the ADSP-BF534/BF5356/BF537processors, a pull down or pull up
may be used. The on-chip boot ROM senses the polarity of this signal and
asserts it by driving it to the opposite state of the external pull up/down.
This PFx number is going to be user-defined and is embedded within the
loader file. The loader utility embeds the number in bits [8:5] of the FLAG
field within every 10-byte header. The loader utility does this by using the
“-pFlag #” command-line switch where number is the intended PF flag
used by the Blackfin slave and has a value between 1 and 15.
� If
Host
(Master SPI
Device)
SPICLK
S_SEL
MOSI
MISO
FLAG /
Interrupt
ADSP-BF533
(Slave SPI)
Device)
SPICLK
SPISS
MOSI
MISO
Figure 2-18. Pin-to-Pin Connections for
ADSP-BF531/BF532/BF533/BF534/ BF536/BF537/BF538/BF539 Processor
SPI Slave Mode
the “-pFlag #” switch is not used, the default value placed within
bits [8:5] of the FLAG is 0, indicating that PF0 is assumed as the
feedback signal to the host. Since PF0 is multiplexed with the
/SPISS pin, which is mandatory for successful SPI slave boot,
always use the “-pFlag #” switch and specify a value other than 0.
2-22 VisualDSP++ 4.5 Loader and Utilities Manual
PFx