VisualDSP++ 4.5 Loader and Utilities Manual - Analog Devices

Blackfin Processor Booting
Load bytes into L1 instruction memory by using the instruction test command
and data registers, as described in the Memory chapter of the
appropriate hardware reference manual. These registers transfer 8-byte
sections of data from external memory to internal L1 instruction memory.
ADSP-BF531/BF532/BF533/BF534/BF536/BF537/
BF538/BF539 Processor Booting
Upon reset, an ADSP-BF531/BF532/BF533/BF534/BF536/BF537/
BF538/BF539 processor jumps to the on-chip boot ROM or jumps to
16-bit external memory for execution (if BMODE = 0) located at
0xEF00 0000. Table 2-2 shows boot modes and execution start addresses
for ADSP-BF531, ADSP-BF532, ADSP-BF533, ADSP-BF538, and
ADSP-BF539 processors.
Table 2-3 shows boot modes for ADSP-BF534/BF536/BF537 processors,
which in addition to all ADSP-BF531/BF532/BF533 processor boot
modes, also can boot from a TWI serial device, a TWI host, and a UART
host.
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