VisualDSP++ 4.5 Loader and Utilities Manual - Analog Devices

I INDEX
Numerics
-64 splitter switch, 7-5
16- to 48-bit word packing, 3-12
32- to 16-bit word packing, 5-6
32- to 8-bit word packing, 5-6
48- to 8-bit word packing, 3-9
4- to 48-bit word packing, 3-15
8- to 48-bit word packing, 3-10, 3-11, 3-12,
4-5, 4-9
A
ACK pin, 3-8, 3-11, 3-13, 4-7
ADDR23-0 address lines, 4-8
ADDR31-0 address lines, 3-10
address records, linear format, A-7
ADSP-2106x/160 processors
ADSP-21060/061/062 boot modes, 3-2, 3-5
ADSP-21065L boot modes, 3-2, 3-6
ADSP-21160 boot modes, 3-2, 3-5
boot sequence, 3-3
direct memory access, See DMA, DMACx
ADSP-21161 processors
boot modes, 4-2, 4-5
boot sequence, 4-3
direct memory access, See DMA, DMACx
multiprocessor support, 4-21
ADSP-2126x/36x/37x processors
boot modes, 5-2, 5-4, 5-8
boot sequence, 5-3
compression support, 5-35
direct memory access, See DMA, DMACx
ADSP-2136x/37x processors
multiprocessor support, 5-33
ADSP-BF531/2/3/4/6/7/8/9 processors
ADSP-BF534/6/7 (only) boot modes, 2-17
boot modes, 2-16
boot sequence, 2-20
boot streams, 2-33
compression support, 2-55
memory ranges, 2-40
on-chip boot ROM, 2-16, 2-19, 2-21, 2-25,
2-40, 2-52
ADSP-BF535 processors
boot modes, 2-2, 2-79
boot sequence, 2-5
boot streams, 2-8, 2-9
memory ranges, 2-14
on-chip boot ROM, 2-2, 2-4, 2-6
second stage loader, 2-6
ADSP-BF561/6 processors
boot modes, 2-42
boot streams, 2-44, 2-46
dual-core architecture, 2-42, 2-44
memory ranges, 2-54
multiprocessor support, 2-50
on-chip boot ROM, 2-42, 2-44, 2-49, 2-50,
2-52, 2-54
.ALIGN directive, 2-15
application
See also blocks of application code
loading, introduction to, 1-14
code start address, 2-70, 2-74, 3-4, 3-18, 4-5
development flow, 1-6
VisualDSP++ 4.5 Loader and Utilities Manual I-1