VisualDSP++ 4.5 Loader and Utilities Manual - Analog Devices

ADSP-2126x/2136x/2137x Processor Booting
address when this DMA completes and
the RTI at 0x80030 is executed. */
IDLE; /* After IDLE, patch then start */
IMASK=0; /* Clear IMASK on way to 0x80004 */
/* ========================================================= */
/* When this final DMA completes, the high-priority SPI interrupt
is latched, which triggers the following chain of events:
1) The IDLE in the delayed branch to completes
2) IMASK is cleared
3) The PC (now 0x80004 due to the “JUMP RESET (db)”) is pushed
on the PC stack and the processor vectors to 0x80030 to
service the interrupt.
Meanwhile, the loader (anticipating this sequence) has automatically
inserted an “RTI” instruction at 0x80030. The user
instruction intended for that address is instead placed
in the FINAL_INIT section-header and has loaded into PX before
the DMA was initiated.)
4) The processor executes the RTI at 0x80030 and vectors to the
address stored on the PC stack (0x80004).
Again, the loader has inserted an instruction into the boot
stream and has placed it at 0x40005 (opcode x39732D802000):
R0=R0-R0,DM(I4,M5)=R9,PM(I12,M13)=R11;
This instruction does the following.
A) Restores the power-up value of SYSCTL (held in R11).
B) Overwrites itself with the instruction “PM(0,I8)=PX;”
The first instruction of FINAL_INIT places the opcode for
this new instruction, 0xB16B00000000, into R9.
C) R0=R0-R0 causes the AZ flag to be set.
This satisfies the termination-condition of the loop set up
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