VisualDSP++ 4.5 Loader and Utilities Manual - Analog Devices

Loader for ADSP-2126x/2136x/2137x SHARC Processors
See the manual for the target SHARC processor peripherals for information
on how data is packed into internal memory during SPI booting for
SPI devices with widths of 32, 16, or 8 bits.
SPI Slave Boot Mode
In SPI slave boot mode, the host processor initiates the booting operation
by activating the SPICLK signal and asserting the SPIDS signal to the active
low state. The 256-word boot kernel is loaded 32 bits at a time, via the
SPI receive shift register. To receive 256 instructions (48-bit words) properly,
the SPI DMA initially loads a DMA count of 384 32-bit words,
which is equivalent to 256 48-bit words.
� The
processor’s SPIDS pin should not be tied low. When in SPI
slave mode, including booting, the SPIDS signal is required to transition
from high to low. SPI slave booting uses the default bit
settings shown in Table 5-5.
Table 5-5. SPI Slave Boot Bit Settings
Bit Setting Comment
SPIEN Set (= 1) SPI enabled
MS Cleared (= 0) Slave device
MSBF Cleared (= 0) LSB first
WL 10, 32-bit SPI Receive Shift register word length
DMISO Set (= 1) MISO MISO disabled
SENDZ Cleared (= 0) Send last word
SPIRCV Set (= 1) Receive DMA enabled
CLKPL Set (= 1) Active low SPI clock
CPHASE Set (= 1) Toggle SPICLK at the beginning of the first bit
VisualDSP++ 4.5 Loader and Utilities Manual 5-9