VisualDSP++ 4.5 Loader and Utilities Manual - Analog Devices

ADSP-21161 Processor Booting
3. Release the bus
4. Execute the loaded instructions
Boot From a Single EPROM
The loader utility can produce boot-loadable files that permit SHARC
processors in a multiprocessor system to boot from a single EPROM. The
BMS signals from each processor may be wire ORed together to drive the
EPROM’s chip select pin. Each processor can boot in turn, according to
its priority. When the last processor has finished booting, it must inform
the other processors (which may be in the idle state) that program execution
can begin (if all processors are to begin executing instructions
simultaneously).
When multiple processors boot from a single EPROM, the processors can
boot identical code or different code from the EPROM. If the processors
load differing code, use a jump table in the loader file (based on processor
ID) to select the code for each processor.
Sequential EPROM Boot
Set the EBOOT pin of the processor with ID# of 1 high for EPROM booting.
The other processors should be configured for host boot (EBOOT=0,
LBOOT=0, and BMS=1), leaving them in the idle state at startup and allowing
the processor with ID=1 to become bus master and boot itself. Connect the
BMS pin of processor #1 only to the EPROM’s chip select pin. When
processor #1 has finished booting, it can boot the remaining processors by
writing to their external port DMA buffer 0 (EPB0) via the multiprocessor
memory space.
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