VisualDSP++ 4.5 Loader and Utilities Manual - Analog Devices

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ADSP-2126x/2136x/2137x Processor Booting Table 5-14. INIT_L16 Block Packing and Zero-Padding (ASCII Format) Original Data Packed into an Even Number of 32-bit Words INIT_L64 Blocks For 64-bit initialization blocks, the data is packed as shown in Table 5-15. Table 5-15. INIT_L64 Block Packing (ASCII Format) Original Data Packed into an Even Number of 32-bit Words -hostwidth 32 16 8 -hostwidth 5-28 VisualDSP++ 4.5 Loader and Utilities Manual 55 00 00 32 16 8 1111222233334444 33334444 33334444 4444 44 11112222 11112222 3333 44 2222 33 1111 33 22 22 11 11
Loader for ADSP-2126x/2136x/2137x SHARC Processors FINAL_INIT Blocks The final 256-instructions of the .ldr file contain the instructions for the IVT. The instructions are initialized by a special self-modifying subroutine in the boot kernel (see Listing 5-3). To support the self-modifying code, the loader utility modifies the FINAL_INIT block as follows: 1. Places a multi-function instruction at the fifth instruction of the block: The loader utility places the instruction R0=R0-R0, DM(I4,M5)=R9, PM(I12,M13)=R11; at 0x80004 for ADSP-2126x processors or 0x90004 for ADSP-2136x/2137x processors. The instruction overwrites whatever instruction is at that address. The opcode for this instruction is 0x39732D802000. 2. Places an RTI instruction in the IVT: The loader utility places an RTI instruction (opcode 0x0B3E00000000) at the first address in the IVT entry associated with the boot-source, either PROM or SPI. Unlike the multifunction instruction placed at 0x80004 (for ADSP-2126x processors) or 0x90004 (for ADSP-2136x/2137x processors), which overwrites the data, the loader utility preserves the user-specified instruction which the RTI replaces. This instruction is stored in the header for FINAL_INIT as shown in Listing 5-2. For PROM boot mode, the RTI is placed at address 0x80050 for ADSP-2126x and at 0x90050 for ADSP-2136x/2137x processors. For all SPI boot modes, the RTI is placed at address 0x80030 for ADSP-2126x and at 0x90036 for ADSP-2136x/2137x processors (high priority SPI interrupt). 3. Saves an IVT instruction in the FINAL_INIT block header. The count and address of a FINAL_INIT block are constant; to avoid any redundancy, the count and address are not placed into the VisualDSP++ 4.5 Loader and Utilities Manual 5-29
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Analog Devices, Inc. One Technology
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CONTENTS PREFACE Purpose of This Ma
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CONTENTS Loader Files Without a Sec
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CONTENTS ADSP-BF535 and ADSP-BF531/
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Contents File Extensions ..........
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Contents Boot Type Selection ......
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PREFACE Thank you for purchasing Vi
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Technical or Customer Support Prefa
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ADSP-21367 ADSP-21368 ADSP21369 ADS
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Preface VisualDSP++ 4.5 C/C++ Compi
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VisualDSP++ Documentation Set Prefa
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1 INTRODUCTION The majority of this
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Loader Command Line Introduction If
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Initialization Code Introduction In
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A brief description of each phase f
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Introduction Download the loadable
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Introduction You can run the loader
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PROM Boot Mode Introduction After r
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Boot Streams Introduction The loade
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2 LOADER/SPLITTER FOR BLACKFIN PROC
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Loader/Splitter for Blackfin Proces
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System Reset Configuration Register
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D7 OUTPUT .LDR FILE 4-BYTE HEADER F
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Second-Stage Loader Restrictions Lo
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SPI Memory Detection Routine Loader
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P0.H = HI(EBIU_SDRRC); R0 = 0x074A(
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� Booting � SDRAM ADSP-BF536 pr
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1-0-Byte Block Header Block Data Lo
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� The Core B Loader/Splitter for
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INITIALIZATION CODE (KERNEL WITH DE
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FLASH MEMORY INIT CODE HEADER INIT
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where: � Command-line File Search
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Blackfin Loader Command-Line Switch
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Using Base Loader Loader/Splitter f
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Table 2-11. Base Load Page Settings
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Using Second-Stage Loader Loader/Sp
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3 LOADER FOR ADSP-2106X/21160 SHARC
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Loader for ADSP-2106x/21160 SHARC P
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Boot Mode Selection Loader for ADSP
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File Searches Loader for ADSP-2106x
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-si-revision #|none|any Loader for
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4 LOADER FOR ADSP-21161 SHARC PROCE
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Loader for ADSP-21161 SHARC Process
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Page 161 and 162: Loader for ADSP-21161 SHARC Process
Page 169 and 170: ADSP-21161 Processor Boot Streams L
Page 171 and 172: To Modify a Boot Kernel Source File
Page 175 and 176: Processor ID Numbers Loader for ADS
Page 179 and 180: File Searches Loader for ADSP-21161
Page 185 and 186: 5 LOADER FOR ADSP-2126X/2136X/2137X
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Page 227 and 228: File Searches Loader for ADSP-2126x
Page 235 and 236: 6 LOADER FOR TIGERSHARC PROCESSORS
Page 237 and 238: � EE-174: Loader for TigerSHARC P
Page 239 and 240: Boot Kernel Modification Loader for
Page 241 and 242: Loader for TigerSHARC Processors el
Page 243 and 244: TigerSHARC Command-Line Switches Lo
Page 245 and 246: Loader for TigerSHARC Processors Ta
Page 247 and 248: 7 SPLITTER FOR SHARC AND TIGERSHARC
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Page 251 and 252: Splitter for SHARC and TigerSHARC P
Page 257 and 258: A FILE FORMATS VisualDSP++ developm
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Page 261 and 262: Build Files File Formats Build file
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Memory Map Files File Formats The l
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Table A-4. End-of-File Record Examp
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This example shows how to include t
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Table A-7. S1 Termination Record Ex
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File Formats A block of data record
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Table A-9. SPORT Data File Example
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B UTILITIES The VisualDSP++ develop
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elf2flt - ELF to BFLT File Converte
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Table B-3. BFLT File Dumper Command
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I INDEX Numerics -64 splitter switc
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BMS pins ADSP-2106x/160 processors,
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data initialization files (.dat), A
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external memory (SHARC processors)
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initialization blocks (Blackfin pro
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loader file formats (ADSP-BF535 pro
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P -p # loader switch for Blackfin,
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shared memory Blackfin processors,
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V .VAR directive, A-3 vector addres
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VisualDSP++ 4.5 Loader and Utilities Manual - Analog Devices

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