VisualDSP++ 4.5 Loader and Utilities Manual - Analog Devices

Loader for ADSP-2126x/2136x/2137x SHARC Processors
SPI master booting uses the default bit settings shown in Table 5-7.
Table 5-7. SPI Master Boot Mode Bit Settings
Bit Setting Comment
SPIEN Set (= 1) SPI enabled
MS Set (= 1) Master device
MSBF Cleared (= 0) LSB first
WL 10 32-bit SPI receive shift register word length
DMISO Cleared (= 0) MISO enabled
SENDZ Set (= 1) Send zeros
SPIRCV Set (= 1) Receive DMA enabled
CLKPL Set (= 1) Active low SPI clock
CPHASE Set (= 1) Toggle SPICLK at the beginning of the first bit
The SPI DMA channel is used when downloading the boot kernel information
to the processor. At reset, the DMA parameter registers are
initialized to the values listed in Table 5-8.
Table 5-8. Parameter Registers Settings for SPI Master Boot
Parameter Register Initialization Value Comment
SPICTL 0x0000 5D06
SPIBAUD 0x0064 CCLK/400 =500 KHz@ 200 MHz
SPIFLG 0xfe01 FLG0 used as slave-select
SPIDMAC 0x0000 0007 Enable receive interrupt on completion
IISPI 0x0008 0000 Start of block 0 normal word memory
IMSPI 0x0000 0001 32-bit data transfers
CSPI 0x0000 0180 0x100 instructions = 0x180 32-bit words
VisualDSP++ 4.5 Loader and Utilities Manual 5-11