VisualDSP++ 4.5 Loader and Utilities Manual - Analog Devices

Loader for ADSP-2106x/21160 SHARC Processors
The EPROM is automatically selected by the BMS pin after reset, and other
memory select pins are disabled. The processor’s DMA controller reads
the 8-bit EPROM words, packs them into 48-bit instruction words, and
transfers them to internal memory until 256 words have been loaded. The
master DMA internal and external count registers (Cx and ECx) decrement
after each EPROM transfer. When both counters reach zero, DMA transfer
has stopped and RTI returns the program counter to the address where
the kernel starts.
� To
EPROM boot a single-processor system, include the executable
on the command-line without a switch. Do not use the -id#exe
switch with ID=0 (see “ADSP-2106x/21160 Processor ID Numbers”
on page 3-24).
The WAIT register UBWM (used for EPROM booting) is initialized at reset to
both internal wait and external acknowledge required. The internal keeper
latch on the ACK pin initially holds acknowledge high (asserted). If
acknowledge is driven low by another device during an EPROM boot, the
keeper latch may latch acknowledge low.
The processor views the deasserted (low) acknowledge as a hold off from
the EPROM. In this condition, wait states are continually inserted, preventing
completion of the EPROM boot. When writing a custom boot
kernel, change the WAIT register early within the boot kernel so UBWM is set
to internal wait mode (01).
Host Boot Mode
ADSP-2106x/21160 processors accept data from a 8- and 16-bit host
microprocessor (or other external device) through the external port EPB0
and pack boot data into 48-bit instructions using an appropriate DMA
channel. The host is selected when the EBOOT and LBOOT inputs are low and
BMS is high. Configured for host booting, the processor enters the slave
mode after reset and waits for the host to download the boot program.
Table 3-10 lists host connections to processors.
VisualDSP++ 4.5 Loader and Utilities Manual 3-11