VisualDSP++ 4.5 Loader and Utilities Manual - Analog Devices

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ADSP-2126x/2136x/2137x Processor Booting 2. The boot kernel runs and loads the application executable code and data. 3. The boot kernel overwrites itself with the first 256 words of the application at the end of the booting process. After that, the application executable code starts running. The boot type selection directs the system to prepare the appropriate boot kernel. Boot Mode Selection Unlike previous SHARC processors, ADSP-2126x/2136x/2137x processors do not have a boot memory select (BMS) pin. On the ADSP-2126x/2136x/2137x processor, the boot type is determined by sampling the state of the BOOTCFGx pins, as described in Table 5-1. A description of each boot type follows in “ADSP-2126x/2136x/2137x Processors Boot Modes”. Table 5-1. ADSP-2126x/2136x Boot Mode Pins BOOT_CFG[1–0] Boot Mode Boot Mode Selection 00 SPI slave -bspislave 01 SPI master (SPI flash, SPI PROM, or a host processor via SPI master mode) -bspiflash -bspiprom -bspimaster 10 EPROM boot via the parallel port -bprom 11 Internal boot. (Not available on all ADSP-2126x processors). Does not use the loader utility 5-4 VisualDSP++ 4.5 Loader and Utilities Manual
Loader for ADSP-2126x/2136x/2137x SHARC Processors ADSP-2126x/2136x/2137x Processors Boot Modes The following sections describe the ADSP-2126x/2136x/2137x processor boot types: “PROM Boot Mode” on page 5-5 “SPI Port Boot Modes” on page 5-8 “Internal Boot Mode” on page 5-17 PROM Boot Mode ADSP-2126x/2136x/2137x processors support an 8-bit boot mode through the parallel port. This mode is used to boot from external 8-bit-wide memory devices. The processor is configured for 8-bit boot mode when the BOOT_CFG1–0 pins = 10. When configured for parallel booting, the parallel port transfers occur with the default bit settings for the PPCTL register (shown in Table 5-2). Table 5-2. PPCTL Register Settings for PROM Boot Mode Bit Setting PPALEPL = 0; ALE is active high PPEN = 1 PPDUR = 10111; (23 core clock cycles per data transfer cycle) PPBHC = 1; insert a bus hold cycle on every access PP16 = 0; external data width = 8 bits PPDEN = 1; use DMA PPTRAN = 0; receive (read) DMA PPBHD = 0; buffer hang enabled VisualDSP++ 4.5 Loader and Utilities Manual 5-5
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Analog Devices, Inc. One Technology
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CONTENTS PREFACE Purpose of This Ma
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CONTENTS Loader Files Without a Sec
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CONTENTS ADSP-BF535 and ADSP-BF531/
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Contents File Extensions ..........
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Contents Boot Type Selection ......
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PREFACE Thank you for purchasing Vi
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Technical or Customer Support Prefa
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ADSP-21367 ADSP-21368 ADSP21369 ADS
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Preface VisualDSP++ 4.5 C/C++ Compi
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VisualDSP++ Documentation Set Prefa
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1 INTRODUCTION The majority of this
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Loader Command Line Introduction If
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Initialization Code Introduction In
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A brief description of each phase f
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Introduction Download the loadable
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Introduction You can run the loader
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PROM Boot Mode Introduction After r
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Boot Streams Introduction The loade
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2 LOADER/SPLITTER FOR BLACKFIN PROC
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Loader/Splitter for Blackfin Proces
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System Reset Configuration Register
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D7 OUTPUT .LDR FILE 4-BYTE HEADER F
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Second-Stage Loader Restrictions Lo
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SPI Memory Detection Routine Loader
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P0.H = HI(EBIU_SDRRC); R0 = 0x074A(
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� Booting � SDRAM ADSP-BF536 pr
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1-0-Byte Block Header Block Data Lo
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� The Core B Loader/Splitter for
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INITIALIZATION CODE (KERNEL WITH DE
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FLASH MEMORY INIT CODE HEADER INIT
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where: � Command-line File Search
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Blackfin Loader Command-Line Switch
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Using Base Loader Loader/Splitter f
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Table 2-11. Base Load Page Settings
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Using Second-Stage Loader Loader/Sp
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3 LOADER FOR ADSP-2106X/21160 SHARC
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Loader for ADSP-2106x/21160 SHARC P
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Boot Mode Selection Loader for ADSP
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Page 137 and 138: Loader for ADSP-2106x/21160 SHARC P
Page 147 and 148: File Searches Loader for ADSP-2106x
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Page 155 and 156: Loader for ADSP-21161 SHARC Process
Page 169 and 170: ADSP-21161 Processor Boot Streams L
Page 171 and 172: To Modify a Boot Kernel Source File
Page 175 and 176: Processor ID Numbers Loader for ADS
Page 179 and 180: File Searches Loader for ADSP-21161
Page 185 and 186: 5 LOADER FOR ADSP-2126X/2136X/2137X
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Page 227 and 228: File Searches Loader for ADSP-2126x
Page 235 and 236: 6 LOADER FOR TIGERSHARC PROCESSORS
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Boot Kernel Modification Loader for
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Loader for TigerSHARC Processors el
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TigerSHARC Command-Line Switches Lo
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Loader for TigerSHARC Processors Ta
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7 SPLITTER FOR SHARC AND TIGERSHARC
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� Most Splitter for SHARC and Tig
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Splitter for SHARC and TigerSHARC P
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A FILE FORMATS VisualDSP++ developm
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Assembly Source Files File Formats
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Build Files File Formats Build file
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Memory Map Files File Formats The l
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Table A-4. End-of-File Record Examp
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This example shows how to include t
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Table A-7. S1 Termination Record Ex
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File Formats A block of data record
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Table A-9. SPORT Data File Example
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B UTILITIES The VisualDSP++ develop
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elf2flt - ELF to BFLT File Converte
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Table B-3. BFLT File Dumper Command
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I INDEX Numerics -64 splitter switc
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BMS pins ADSP-2106x/160 processors,
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data initialization files (.dat), A
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external memory (SHARC processors)
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initialization blocks (Blackfin pro
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loader file formats (ADSP-BF535 pro
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P -p # loader switch for Blackfin,
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shared memory Blackfin processors,
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V .VAR directive, A-3 vector addres
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VisualDSP++ 4.5 Loader and Utilities Manual - Analog Devices

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