VisualDSP++ 4.5 Loader and Utilities Manual - Analog Devices

Loader/Splitter for Blackfin Processors
ADSP-BF534/BF536/BF537 TWI Master Boot Mode
(BMODE = 101)
The Blackfin processor selects the slave EEPROM with the unique ID
0xA0, and submits successive read commands to the device starting at two
byte internal address 0x0000 and begins clocking data into the processor.
The serial EEPROM must be two-byte addressable. The EEPROM’s
device select bits A2–0 must be 0s (tied low). The I 2 C EPROM device
should comply with Philips I2C Bus Specification version 2.1 and should
have the capability to auto increment its internal address counter such that
the contents of the memory device can be read sequentially (see
Figure 2-20).
The TWI controller is programmed so as to generate a 30% duty cycle
clock in accordance with the I 2 C clock specification for fast-mode
operation.
� In
both TWI master and slave boot modes, the upper 256 bytes
starting at address 0xFF90 3F00 must not be used. The boot ROM
code uses this space for the TWI boot modes to temporarily hold
the serial data which is then transferred to L1 instruction memory
using DMA.
Figure 2-20. TWI Master Boot Mode
VisualDSP++ 4.5 Loader and Utilities Manual 2-27