VisualDSP++ 4.5 Loader and Utilities Manual - Analog Devices

ADSP-2126x/2136x/2137x Processor Booting
SPI Master and SPI Slave. When loading to other slave devices, the SPI
master and SPI slave boot types do not need bit reversing necessarily. For
SPI slave and SPI master boots to non-PROM devices, the same default
exists (bit-reversed); however, the host (master or slave) can simply be
configured to transmit LSB first.
Initial Word Option for SPI Master Boot Modes
Before final formatting (binary, include, etc.) the loader must prepends
the word 0xA5 to the beginning of the byte stream. During SPI master
booting, the SPI port discards the first byte read from the SPI.
SPI PROM. For the SPI PROM boot type, the word 0xA5 prepended to
the stream is one byte in length. SPI PROMs receives a 24-bit read command
before any data is sent to the processor, the processor then discards
the first byte it receives after this 24-bit opcode is sent (totaling one 32-bit
word).
SPI Master. For the SPI master boot type, the word 0xA5000000
prepended to the stream is 32 bits in length. An SPI host configured as a
slave begins sending data to the processor while the processor is sending
the 24-bit PROM read opcode. These 24-bits must be zero-filled because
the processor discards the first 32-bit word that it receives from the slave.
� The
0xA5 byte is only required for SPI master boot mode.
Figure 5-2 and Table 5-9 illustrates the first 32-bit word for both the SPI
PROM and SPI master cases.
With bit reversing for SPI master boot mode, the 32-bit word is handled
according to the host width. With bit reversing for SPI PROM boot, the
8-bit word is reversed as a byte and prepended (see Table 5-10).
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