VisualDSP++ 4.5 Loader and Utilities Manual - Analog Devices

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INDEX R -r #, splitter switch, 7-6 -ram, splitter switch, 7-5, 7-6 RBAM bit, 4-7 RBWS bit, 4-7 RD pin, 3-10, 4-8 references, file formats, A-17 RESET interrupt service routine, 2-4, 2-19, 2-43, 4-12 pin, 3-9, 4-8, 4-11, 6-3 reset processor, introduction to, 1-13, 1-14 ADSP-2106x/160 processors, 3-3, 3-8, 3-11, 3-12, 3-16 ADSP-21161 processors, 4-3, 4-6, 4-7, 4-9, 4-10, 4-13, 4-15 ADSP-2126x/36x/37x processors, 5-3, 5-10, 5-11, 5-17, 5-19 ADSP-BF561/6 processors, 2-42, 2-43, 2-79 Blackfin processors, 2-2, 2-6, 2-16 dual-core Blackfin processors, 2-42 SHARC processors, 5-6 TigerSHARC processors, 6-2, 6-3, 6-4 vector addresses, 3-4, 3-9, 3-14, 4-20, 5-21 vector routine, 2-82, 4-9 reset vector addresses, 3-9 resistors (pull-up), 2-21, 2-24, 2-25, 6-3 restrictions, second-stage loader, 2-15 -retainSecondStageKernel, loader switch for SHARC, 5-47 ROM memory images as ASCII text files, A-15 memory sections, 7-5 setting splitter options (Blackfin processors), 2-79 splitter, See splitter -romsplitter, loader switch for Blackfin, 2-69, 2-71 Rx registers, 2-49, 2-52, 3-13 RXSPI register, 5-8 RXSR register, 5-8 RXx registers, 5-10 S s1 (Motorola EXORciser) file format, 6-9, 7-6, A-11 s2 (Motorola EXORMAX) file format, 6-9, 7-6, A-11 s3 (Motorola 32-bit) file format, 6-9, 7-6, A-11 scratchpad memory (Blackfin processors) ADSP-BF535 processors, 2-14 ADSP-BF561/6 processors, 2-55 SDCTL register, 4-18, 5-20 SDRAM memory (ADSP-2106x/160 processors), 3-17 SDRAM memory (Blackfin processors) ADSP-BF531/2/3/4/6/7/8/9 processors, 2-35, 2-38, 2-41 ADSP-BF535 processors, 2-6, 2-14, 2-15 ADSP-BF561/6 processors, 2-49, 2-55 SDRDIV register, 4-18, 5-20 second-stage loader ADSP-BF535 processors, 1-14, 2-6, 2-8, 2-13, 2-14, 2-15 ADSP-BF561/6 processors, 2-49, 2-50 creating from VisualDSP++, 2-78 setting options, 2-74, 2-76 source files (ADSP-BF535 processors), 2-78 SENDZ bit, 5-9, 5-11 sequential EPROM boot, 4-22 serial peripheral interface, See SPI I-14 VisualDSP++ 4.5 Loader and Utilities Manual
shared memory Blackfin processors, 2-50, 2-55 file format (.sm), 2-50, 2-64, 6-8, A-6, A-16 in compressed .ldr files, 5-36, 5-39 omitting from loader file, 3-28, 4-28 shift register, See RX registers -ShowEncryptionMessage, loader switch for Blackfin, 2-71 silicon revision, setting, 2-71, 3-31, 4-31, 5-48, 6-11, 7-8 simulators, for boot simulation, 1-9 single-processor systems, 3-24, 4-23, 6-6, 6-9, 7-2 -si-revision #|none|any loader switch for Blackfin, 2-71 loader switch for SHARC, 3-31, 4-31, 5-48 loader switch for TigerSHARC, 6-11 splitter switch, 7-8 slave processors, 1-9, 1-13, 5-10 .s_# (Motorola S-record) files, 7-4, A-11 .sm (shared memory) files, 2-64, 3-28, 4-28, 6-8, A-6, A-16 software reset, 1-12, 2-4, 2-5, 2-19, 2-43 source file formats assembly text (.asm), A-3 C/C++ text (.c, .cpp, .cxx), A-2 SPIBAUD register, 5-11 SPI boot modes (SHARC processors) ADSP-21161 processors, 4-2, 4-4, 4-14 ADSP-2126x/36x/37x processors, 5-8, 5-13, 5-21, 5-29 SPICLK register, 2-24, 5-9, 5-10, 5-13, 5-17 SPICTL register, 2-24, 4-15, 5-10, 5-11 SPIDMAC register, 5-10, 5-11 SPIDS signal, 5-9 INDEX SPI EEPROM boot mode (Blackfin processors) ADSP-BF535 processors, 2-2, 2-3, 2-6, 2-9, 2-10 ADSP-BF561/6 processors, 2-42, 2-49 SPIEN bit, 5-9, 5-11 SPI flash boot mode (ADSP-2126x/36x/37x processors), 5-16 SPIFLG register, 5-11 SPI host boot mode (ADSP-2126x/36x/37x processors), 5-17 SPI master boot modes ADSP-2126x/36x/37x processors, 5-8, 5-10, 5-14, 5-18 ADSP-BF531/2/3/8/9 processors, 2-17, 2-23 ADSP-BF534/6/7 processors, 2-17, 2-23 See also SPI flash, SPI ROM, host processor master boot modes SPI memory baud rate, See baud rate control registers, 2-24 detection routine, 2-25 host devices, 2-21, 2-23 slave devices, 5-12 supported devices, 2-24 SPI PROM boot mode (ADSP-2126x/36x/37x processors), 5-13, 5-14, 5-16 SPIRCV bit, 5-9, 5-11 SPIRx register, 4-2, 4-14, 4-15 SPI slave boot mode (ADSP-2126x/36x/37x processors), 5-8, 5-9, 5-14 SPI slave boot mode (Blackfin processors) ADSP-BF531/2/3/8/9 processors, 2-17, 2-21 ADSP-BF534/6/7 processors, 2-17, 2-21 VisualDSP++ 4.5 Loader and Utilities Manual I-15
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Analog Devices, Inc. One Technology
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CONTENTS PREFACE Purpose of This Ma
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CONTENTS Loader Files Without a Sec
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CONTENTS ADSP-BF535 and ADSP-BF531/
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Contents File Extensions ..........
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Contents Boot Type Selection ......
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PREFACE Thank you for purchasing Vi
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Technical or Customer Support Prefa
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ADSP-21367 ADSP-21368 ADSP21369 ADS
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Preface VisualDSP++ 4.5 C/C++ Compi
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VisualDSP++ Documentation Set Prefa
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1 INTRODUCTION The majority of this
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Loader Command Line Introduction If
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Initialization Code Introduction In
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A brief description of each phase f
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Introduction Download the loadable
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Introduction You can run the loader
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PROM Boot Mode Introduction After r
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Boot Streams Introduction The loade
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2 LOADER/SPLITTER FOR BLACKFIN PROC
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Loader/Splitter for Blackfin Proces
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System Reset Configuration Register
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D7 OUTPUT .LDR FILE 4-BYTE HEADER F
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Second-Stage Loader Restrictions Lo
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SPI Memory Detection Routine Loader
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P0.H = HI(EBIU_SDRRC); R0 = 0x074A(
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� Booting � SDRAM ADSP-BF536 pr
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1-0-Byte Block Header Block Data Lo
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� The Core B Loader/Splitter for
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INITIALIZATION CODE (KERNEL WITH DE
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FLASH MEMORY INIT CODE HEADER INIT
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where: � Command-line File Search
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Blackfin Loader Command-Line Switch
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Using Base Loader Loader/Splitter f
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Table 2-11. Base Load Page Settings
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Using Second-Stage Loader Loader/Sp
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3 LOADER FOR ADSP-2106X/21160 SHARC
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Loader for ADSP-2106x/21160 SHARC P
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Boot Mode Selection Loader for ADSP
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File Searches Loader for ADSP-2106x
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-si-revision #|none|any Loader for
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4 LOADER FOR ADSP-21161 SHARC PROCE
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Loader for ADSP-21161 SHARC Process
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ADSP-21161 Processor Boot Streams L
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To Modify a Boot Kernel Source File
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Processor ID Numbers Loader for ADS
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File Searches Loader for ADSP-21161
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5 LOADER FOR ADSP-2126X/2136X/2137X
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Loader for ADSP-2126x/2136x/2137x S
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File Searches Loader for ADSP-2126x
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6 LOADER FOR TIGERSHARC PROCESSORS
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� EE-174: Loader for TigerSHARC P
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Boot Kernel Modification Loader for
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Loader for TigerSHARC Processors el
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Page 245 and 246: Loader for TigerSHARC Processors Ta
Page 247 and 248: 7 SPLITTER FOR SHARC AND TIGERSHARC
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Page 257 and 258: A FILE FORMATS VisualDSP++ developm
Page 259 and 260: Assembly Source Files File Formats
Page 261 and 262: Build Files File Formats Build file
Page 263 and 264: Memory Map Files File Formats The l
Page 265 and 266: Table A-4. End-of-File Record Examp
Page 267 and 268: This example shows how to include t
Page 269 and 270: Table A-7. S1 Termination Record Ex
Page 271 and 272: File Formats A block of data record
Page 273 and 274: Table A-9. SPORT Data File Example
Page 275 and 276: B UTILITIES The VisualDSP++ develop
Page 277 and 278: elf2flt - ELF to BFLT File Converte
Page 279 and 280: Table B-3. BFLT File Dumper Command
Page 281 and 282: I INDEX Numerics -64 splitter switc
Page 283 and 284: BMS pins ADSP-2106x/160 processors,
Page 285 and 286: data initialization files (.dat), A
Page 287 and 288: external memory (SHARC processors)
Page 289 and 290: initialization blocks (Blackfin pro
Page 291 and 292: loader file formats (ADSP-BF535 pro
Page 293: P -p # loader switch for Blackfin,
Page 297 and 298: V .VAR directive, A-3 vector addres
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VisualDSP++ 4.5 Loader and Utilities Manual - Analog Devices

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