VisualDSP++ 4.5 Loader and Utilities Manual - Analog Devices

ADSP-2106x/21160 Processor Booting
5. The processor begins 8-bit DMA transfers from the EPROM to
internal memory using the following external port data bus lines:
D23—16 for ADSP-21060/61/62 processors
D7—0 for ADSP-21065L processors
D39—32 for ADSP-21160 processors
6. Data transfers begin and increment after each access. The external
address lines (ADDR31—0) start at:
0x40 0000 for ADSP-21060/61/62 processors
0x00 0000 for ADSP-21065L processors
0x80 0000 for ADSP-21160 processors
7. The processor RD pin asserts as in a normal memory access, with six
wait states (seven cycles).
8. After finishing DMA transfers to load the boot kernel into the processor,
the BSO bit is cleared in the SYSCON register, deactivating the
BMS pin and activating normal external memory select.
The boot kernel uses three copies of SYSCON—one that contains the
original value of SYSCON, a second that contains SYSCON with the
BSO bit set (allowing the processor to gain access to the boot
EPROM), and a third with the BSO bit cleared.
When BSO=1, the EPROM packing mode bits in the DMACx control
register are ignored and 8- to 48-bit packing is forced. (8-bit packing
is available only during EPROM booting or when BSO is set.)
When an external port DMA channel is being used in conjunction
with the BSO bit, none of the other three channels may be used. In
this mode, BMS is not asserted by a core processor access but only by
a DMA transfer. This allows the boot kernel to perform other
external accesses to non-boot memory.
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