VisualDSP++ 4.5 Loader and Utilities Manual - Analog Devices

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INDEX H -h|help loader switch for Blackfin, 2-66 loader switch for SHARC, 3-29, 4-29, 5-45 loader switch for TigerSHARC, 6-9 HBG pin, 3-13 HBR pin, 4-12 HBW bits, 3-12 header files (.h), A-4 See also global headers header records byte-stacked format (.stk), A-14 s-record format (.s_#), A-11 hexadecimal format, See .h_# (Intel hex-32) file format hexutil utility, B-2 .h_# (Intel hex-32) file format, 6-9, 7-4, 7-6, A-7, A-13 -HoldTime #, loader switch for Blackfin, 2-66 hold time cycles, 2-6, 2-44 host boot mode, introduction to, 1-13 host boot mode (SHARC processors) ADSP-2106x/160 processors, 3-2, 3-6, 3-11, 3-13, 3-24 ADSP-21161 processors, 4-2, 4-9 ADSP-2126x/36x/37x processors, 5-8, 5-10, 5-17 host boot mode (TigerSHARC processors), 6-2, 6-4, 6-9 -hostwidth #, loader switch for SHARC, 4-29, 5-15, 5-26, 5-45 HPM bit, 3-12 I ICPP register, 5-6 -id#exe=filename loader switch for SHARC, 3-24, 3-29, 4-23, 4-29, 5-45 loader switch for TigerSHARC, 6-6, 6-9 -id#exe=N, loader switch for SHARC, 4-29 IDLE instruction, 3-4, 3-14, 3-19, 3-20, 4-6, 4-10, 4-13, 4-15, 5-21 idle state, 2-44, 6-3 -id#ref=N, loader switch for SHARC, 3-29, 5-46 ignore blocks (Blackfin processors) ADSP-BF531/2/3/4/6/7/8/9 processors, 2-35 ADSP-BF561/6 processors, 2-45 IIEP0 register, 3-8, 4-8, 4-11 IILB0 register, 4-14 IIPP register, 5-6 IISPI register, 5-10, 5-11 IISRX register, 4-16 IIVT bit, 3-22, 4-21, 5-22 IIx register, 3-8, 3-9, 3-15 image files, See PROM, non-bootable files IMASK register, 3-13, 3-14, 3-15 IMDW register, 3-14, 5-30 IMEP0 register, 3-8, 4-8, 4-11 IMLB0 register, 4-14 IMPP register, 5-6 IMSPI register, 5-10, 5-11 IMSRX register, 4-16 IMx register, 3-8, 3-9 include file format, 6-9, A-10 -init filename, loader switch for Blackfin, 2-35, 2-52, 2-60, 2-67, 2-70 initialization external memory, 6-10 file inclusion, 2-67, 2-75 initialization blocks (ADSP-2126x/36x/37x processors), 5-23, 5-26, 5-27, 5-28, 5-30 I-8 VisualDSP++ 4.5 Loader and Utilities Manual
initialization blocks (Blackfin processors) ADSP-BF531/2/3/4/6/7/8/9 processors, 2-21, 2-35, 2-36, 2-53 ADSP-BF561/6 processors, 2-49, 2-50, 2-53 code example, 2-38, 2-53 initial word option (SHARC processors), 5-14, 5-15 INIT_L16 blocks, 5-27 INIT_L48 blocks, 5-26 INIT_L64 blocks, 5-28 input file formats, See source file formats input files executable (.dxe) files, 2-64, 3-26, 4-25, 5-42, 6-8 extracting memory sections from, 7-5, 7-6 in multiprocessor systems, 6-6 instruction SRAM (Blackfin processors) ADSP-BF531/2/3/4/6/7/8/9 processors, 2-40 ADSP-BF535 processors, 2-14 ADSP-BF561/6 processors, 2-50, 2-54 Intel hex-32 file format, 2-66, 6-9, A-7 internal boot mode (SHARC processors), 5-17 internal memory, boot-loadable file execution, 1-9 internal vector tables, 3-22, 4-21 interrupt vector location, 4-9, 4-12 interrupt vector tables, 3-22, 4-21, 5-17, 5-18, 5-22, 5-29, 5-30 IOP registers, 3-12, 3-13 IRQ vector, 3-8, 3-9 INDEX IVG15 lowest priority interrupt, 2-4, 2-19, 2-35, 2-43 K -kb prom|flash|spi|spislave|UART|TWI|F IFO, loader switch for Blackfin, 2-67 -kenc dll_filename, loader switch for Blackfin, 2-68 Kernel (Load) page (Blackfin processors), 2-77 kernels (ADSP-2106x/160 processors) boot sequence, 3-3, 3-16 default source files, 3-16, 3-21 loading to processor, 3-10, 3-13 modifying, 3-19 rebuilding, 3-22 replacing with application code, 3-18 specifying user kernel, 3-30 kernels (ADSP-21161 processors) boot sequence, 4-3 default source files, 4-16, 4-19 modifying, 4-18, 4-19 rebuilding, 4-18, 4-19 kernels (ADSP-2126x/36x/37x processors) boot sequence, 5-3, 5-19 compression/decompression, 5-35, 5-36, 5-40 default source files, 5-19 loading to processor, 5-9, 5-13 modifying, 5-20 omitting in output, 5-17 rebuilding, 5-20, 5-21 VisualDSP++ 4.5 Loader and Utilities Manual I-9
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Analog Devices, Inc. One Technology
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CONTENTS PREFACE Purpose of This Ma
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CONTENTS Loader Files Without a Sec
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CONTENTS ADSP-BF535 and ADSP-BF531/
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Contents File Extensions ..........
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Contents Boot Type Selection ......
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PREFACE Thank you for purchasing Vi
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Technical or Customer Support Prefa
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ADSP-21367 ADSP-21368 ADSP21369 ADS
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Preface VisualDSP++ 4.5 C/C++ Compi
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VisualDSP++ Documentation Set Prefa
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1 INTRODUCTION The majority of this
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Loader Command Line Introduction If
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Initialization Code Introduction In
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A brief description of each phase f
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Introduction Download the loadable
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Introduction You can run the loader
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PROM Boot Mode Introduction After r
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Boot Streams Introduction The loade
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2 LOADER/SPLITTER FOR BLACKFIN PROC
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Loader/Splitter for Blackfin Proces
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System Reset Configuration Register
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D7 OUTPUT .LDR FILE 4-BYTE HEADER F
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Second-Stage Loader Restrictions Lo
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SPI Memory Detection Routine Loader
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P0.H = HI(EBIU_SDRRC); R0 = 0x074A(
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� Booting � SDRAM ADSP-BF536 pr
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1-0-Byte Block Header Block Data Lo
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� The Core B Loader/Splitter for
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INITIALIZATION CODE (KERNEL WITH DE
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FLASH MEMORY INIT CODE HEADER INIT
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where: � Command-line File Search
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Blackfin Loader Command-Line Switch
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Using Base Loader Loader/Splitter f
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Table 2-11. Base Load Page Settings
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Using Second-Stage Loader Loader/Sp
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3 LOADER FOR ADSP-2106X/21160 SHARC
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Loader for ADSP-2106x/21160 SHARC P
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Boot Mode Selection Loader for ADSP
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File Searches Loader for ADSP-2106x
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-si-revision #|none|any Loader for
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4 LOADER FOR ADSP-21161 SHARC PROCE
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Loader for ADSP-21161 SHARC Process
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ADSP-21161 Processor Boot Streams L
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To Modify a Boot Kernel Source File
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Processor ID Numbers Loader for ADS
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File Searches Loader for ADSP-21161
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5 LOADER FOR ADSP-2126X/2136X/2137X
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Loader for ADSP-2126x/2136x/2137x S
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File Searches Loader for ADSP-2126x
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6 LOADER FOR TIGERSHARC PROCESSORS
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Page 239 and 240: Boot Kernel Modification Loader for
Page 241 and 242: Loader for TigerSHARC Processors el
Page 243 and 244: TigerSHARC Command-Line Switches Lo
Page 245 and 246: Loader for TigerSHARC Processors Ta
Page 247 and 248: 7 SPLITTER FOR SHARC AND TIGERSHARC
Page 249 and 250: � Most Splitter for SHARC and Tig
Page 251 and 252: Splitter for SHARC and TigerSHARC P
Page 257 and 258: A FILE FORMATS VisualDSP++ developm
Page 259 and 260: Assembly Source Files File Formats
Page 261 and 262: Build Files File Formats Build file
Page 263 and 264: Memory Map Files File Formats The l
Page 265 and 266: Table A-4. End-of-File Record Examp
Page 267 and 268: This example shows how to include t
Page 269 and 270: Table A-7. S1 Termination Record Ex
Page 271 and 272: File Formats A block of data record
Page 273 and 274: Table A-9. SPORT Data File Example
Page 275 and 276: B UTILITIES The VisualDSP++ develop
Page 277 and 278: elf2flt - ELF to BFLT File Converte
Page 279 and 280: Table B-3. BFLT File Dumper Command
Page 281 and 282: I INDEX Numerics -64 splitter switc
Page 283 and 284: BMS pins ADSP-2106x/160 processors,
Page 285 and 286: data initialization files (.dat), A
Page 287: external memory (SHARC processors)
Page 291 and 292: loader file formats (ADSP-BF535 pro
Page 293 and 294: P -p # loader switch for Blackfin,
Page 295 and 296: shared memory Blackfin processors,
Page 297 and 298: V .VAR directive, A-3 vector addres
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VisualDSP++ 4.5 Loader and Utilities Manual - Analog Devices

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