VisualDSP++ 4.5 Loader and Utilities Manual - Analog Devices

P
-p #
loader switch for Blackfin, 2-70
loader switch for TigerSHARC, 6-10
packing boot data, 4-2, 6-2
PACKING() command, 5-7
-paddress, loader switch for SHARC, 3-30,
4-30, 5-47
parallel ports, 5-6
parallel/serial PROM devices, 1-13
-pflag PF|PG|PH #, loader switch for
Blackfin, 2-22, 2-70
PFx signals, 2-21, 2-24, 2-70
placement rules, of the command-line,
2-63, 6-6
PMODE register, 3-9, 3-12, 4-7, 4-11
-pm splitter switch, 7-5
PP16 bit, 5-5
PPALEPL bit, 5-5
PPBHC bit, 5-5
PPBHD bit, 5-5
PPCTL register, 5-5, 5-6
PPDEN bit, 5-5
PPDUR bit, 5-5
PPEN bit, 5-5
PPTRAN bit, 5-5
processor IDs, 3-23, 3-24, 4-22, 4-23, 6-6,
6-9
assigning to .dxe file, 3-29, 4-29, 5-45
pointing to jump table, 3-29, 4-29
processor-loadable files, introduction to,
1-12
processor type bits (Blackfin boot streams),
2-35
INDEX
-proc part_number
loader switch for Blackfin, 2-71
loader switch for SHARC, 3-30, 4-30,
5-47
loader switch for TigerSHARC, 6-9,
6-10
splitter switch, 7-7
program counter settings
(ADSP-2106x/160 processors), 3-12
program development flow, 1-6
program memory sections (splitter), 7-3,
7-5
Project Options dialog box, 1-11, 2-62,
2-73, 2-74, 5-20, 6-4, 6-5
PROM
boot mode, introduction to, 1-13
downloading boot-loadable files, 1-9
memory devices, 5-16, A-7
PROM boot mode, ADSP-2126x/36x/37x
processors, 5-5, 5-21, 5-29
PROM boot mode, TigerSHARC
processors, 6-4, 6-9
PROM/flash boot mode (Blackfin
processors)
ADSP-535 processors, 2-66
ADSP-BF531/2/3/4/6/7/8/9 processors,
2-17, 2-53
ADSP-BF535 processors, 2-2, 2-9, 2-10,
2-15
ADSP-BF561/6 processors, 2-49, 2-53
ADSP-BF561/BF566 processors, 2-42
PROM (image) files
creating from command line, 7-2
creating from GUI, 7-9
ignoring ROM sections, 7-5
specifying format, 7-6
specifying name, 7-5
specifying width, 7-6
pull-up resistors, 4-7
Px register, 3-18, 5-30
VisualDSP++ 4.5 Loader and Utilities Manual I-13