VisualDSP++ 4.5 Loader and Utilities Manual - Analog Devices

Blackfin Processor Booting
(p5:0) = [SP++];
/* MAKE SURE NOT TO RESTORE
R0 for flash/PROM Boot, R3 for SPI Boot */
(r7:0) = [SP++];
RETS = [SP++];
ASTAT = [SP++];
/**************************************************************/
RTS;
ADSP-BF561/BF566 Processor Memory Ranges
The on-chip boot ROM of the ADSP-BF561/BF566 processor can load a
full application to the various memories of both cores. Booting is allowed
to the following memory ranges. The boot ROM clears these memory
ranges before booting in a new application.
Core A
� L1 instruction SRAM (0xFFA0 0000 – 0xFFA0 3FFF)
� L1 instruction cache/SRAM (0xFFA1 0000 – 0xFFA1 3FFF)
� L1 data bank A SRAM (0xFF80 0000 – 0xFF80 3FFF)
� L1 data bank A cache/SRAM (0xFF80 4000 – 0xFF80 7FFF)
� L1 data bank B SRAM (0xFF90 0000 – 0xFF90 3FFF)
� L1 data bank B cache/SRAM (0xFF90 4000 – 0xFF90 7FFF)
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