VisualDSP++ 4.5 Loader and Utilities Manual - Analog Devices

Loader for ADSP-21161 SHARC Processors
ADSP-21161 Processor Interrupt Vector Table
If the ADSP-21161 processor is booted from an external source (EPROM,
host, link port, or SPI), the interrupt vector table is located in internal
memory. If the processor is not booted and executes from external memory
(no-boot mode), the vector table must be located in external memory.
The IIVT bit in the SYSCON control register can be used to override the
booting mode in determining where the interrupt vector table is located.
If the processor is not booted (no-boot mode), setting IIVT to 1 selects an
internal vector table, and setting IIVT to zero selects an external vector
table. If the processor is booted from an external source (any boot mode
other than no-boot), IIVT has no effect. The default initialization value of
IIVT is zero.
ADSP-21161 Multi-Application (Multi-DXE)
Management
Currently, the loader utility generates single-processor loader files for
host, link, and SPI port boot. The loader utility supports multiprocessor
EPROM boot only. The application code must be modified to properly
set up multiprocessor booting in host, link, and SPI port boot modes.
There are two methods by which a multiprocessor system can be booted:
“Boot From a Single EPROM”
“Sequential EPROM Boot”
Regardless of the method, the processors perform the following steps.
1. Arbitrate for the bus
2. Upon becoming bus master, DMA the 256-word boot stream
VisualDSP++ 4.5 Loader and Utilities Manual 4-21