VisualDSP++ 4.5 Loader and Utilities Manual - Analog Devices

More documents

Recommendations

Info

ADSP-2126x/2136x/2137x Processor Booting 2. The boot kernel runs and loads the application executable code and data. 3. The boot kernel overwrites itself with the first 256 words of the application at the end of the booting process. After that, the application executable code starts running. The boot type selection directs the system to prepare the appropriate boot kernel. Boot Mode Selection Unlike previous SHARC processors, ADSP-2126x/2136x/2137x processors do not have a boot memory select (BMS) pin. On the ADSP-2126x/2136x/2137x processor, the boot type is determined by sampling the state of the BOOTCFGx pins, as described in Table 5-1. A description of each boot type follows in “ADSP-2126x/2136x/2137x Processors Boot Modes”. Table 5-1. ADSP-2126x/2136x Boot Mode Pins BOOT_CFG[1–0] Boot Mode Boot Mode Selection 00 SPI slave -bspislave 01 SPI master (SPI flash, SPI PROM, or a host processor via SPI master mode) -bspiflash -bspiprom -bspimaster 10 EPROM boot via the parallel port -bprom 11 Internal boot. (Not available on all ADSP-2126x processors). Does not use the loader utility 5-4 VisualDSP++ 4.5 Loader and Utilities Manual
Loader for ADSP-2126x/2136x/2137x SHARC Processors ADSP-2126x/2136x/2137x Processors Boot Modes The following sections describe the ADSP-2126x/2136x/2137x processor boot types: “PROM Boot Mode” on page 5-5 “SPI Port Boot Modes” on page 5-8 “Internal Boot Mode” on page 5-17 PROM Boot Mode ADSP-2126x/2136x/2137x processors support an 8-bit boot mode through the parallel port. This mode is used to boot from external 8-bit-wide memory devices. The processor is configured for 8-bit boot mode when the BOOT_CFG1–0 pins = 10. When configured for parallel booting, the parallel port transfers occur with the default bit settings for the PPCTL register (shown in Table 5-2). Table 5-2. PPCTL Register Settings for PROM Boot Mode Bit Setting PPALEPL = 0; ALE is active high PPEN = 1 PPDUR = 10111; (23 core clock cycles per data transfer cycle) PPBHC = 1; insert a bus hold cycle on every access PP16 = 0; external data width = 8 bits PPDEN = 1; use DMA PPTRAN = 0; receive (read) DMA PPBHD = 0; buffer hang enabled VisualDSP++ 4.5 Loader and Utilities Manual 5-5
Page 1 and 2:
Analog Devices, Inc. One Technology
Page 3 and 4:
CONTENTS PREFACE Purpose of This Ma
Page 5 and 6:
CONTENTS Loader Files Without a Sec
Page 7 and 8:
CONTENTS ADSP-BF535 and ADSP-BF531/
Page 9 and 10:
Contents File Extensions ..........
Page 11 and 12:
Contents Boot Type Selection ......
Page 13 and 14:
PREFACE Thank you for purchasing Vi
Page 15 and 16:
Technical or Customer Support Prefa
Page 17 and 18:
ADSP-21367 ADSP-21368 ADSP21369 ADS
Page 19 and 20:
Preface VisualDSP++ 4.5 C/C++ Compi
Page 21 and 22:
VisualDSP++ Documentation Set Prefa
Page 23 and 24:
1 INTRODUCTION The majority of this
Page 25 and 26:
Loader Command Line Introduction If
Page 27 and 28:
Initialization Code Introduction In
Page 29 and 30:
A brief description of each phase f
Page 31 and 32:
Introduction Download the loadable
Page 33 and 34:
Introduction You can run the loader
Page 35 and 36:
PROM Boot Mode Introduction After r
Page 37 and 38:
Boot Streams Introduction The loade
Page 39 and 40:
2 LOADER/SPLITTER FOR BLACKFIN PROC
Page 41 and 42:
Loader/Splitter for Blackfin Proces
Page 43 and 44:
System Reset Configuration Register
Page 45 and 46:
Page 47 and 48:
Page 49 and 50:
D7 OUTPUT .LDR FILE 4-BYTE HEADER F
Page 51 and 52:
Page 53 and 54:
Second-Stage Loader Restrictions Lo
Page 55 and 56:
Page 57 and 58:
Page 59 and 60:
Page 61 and 62:
Page 63 and 64:
SPI Memory Detection Routine Loader
Page 65 and 66:
Page 67 and 68:
Page 69 and 70:
Page 71 and 72:
Page 73 and 74:
Page 75 and 76:
Page 77 and 78:
P0.H = HI(EBIU_SDRRC); R0 = 0x074A(
Page 79 and 80:
� Booting � SDRAM ADSP-BF536 pr
Page 81 and 82:
Page 83 and 84:
Page 85 and 86:
1-0-Byte Block Header Block Data Lo
Page 87 and 88:
Page 89 and 90:
Page 91 and 92:
Page 93 and 94:
� The Core B Loader/Splitter for
Page 95 and 96:
INITIALIZATION CODE (KERNEL WITH DE
Page 97 and 98:
Page 99 and 100:
FLASH MEMORY INIT CODE HEADER INIT
Page 101 and 102:
where: � Command-line File Search
Page 103 and 104:
Blackfin Loader Command-Line Switch
Page 105 and 106:
Page 107 and 108:
Page 109 and 110:
Page 111 and 112:
Using Base Loader Loader/Splitter f
Page 113 and 114:
Table 2-11. Base Load Page Settings
Page 115 and 116:
Using Second-Stage Loader Loader/Sp
Page 117 and 118:
Page 119 and 120:
Page 121 and 122:
3 LOADER FOR ADSP-2106X/21160 SHARC
Page 123 and 124:
Loader for ADSP-2106x/21160 SHARC P
Page 125 and 126:
Boot Mode Selection Loader for ADSP
Page 127 and 128:
Page 129 and 130:
Page 131 and 132:
Page 133 and 134:
Page 135 and 136:
Page 137 and 138: Loader for ADSP-2106x/21160 SHARC P
Page 147 and 148: File Searches Loader for ADSP-2106x
Page 151 and 152: -si-revision #|none|any Loader for
Page 153 and 154: 4 LOADER FOR ADSP-21161 SHARC PROCE
Page 155 and 156: Loader for ADSP-21161 SHARC Process
Page 169 and 170: ADSP-21161 Processor Boot Streams L
Page 171 and 172: To Modify a Boot Kernel Source File
Page 175 and 176: Processor ID Numbers Loader for ADS
Page 179 and 180: File Searches Loader for ADSP-21161
Page 185 and 186: 5 LOADER FOR ADSP-2126X/2136X/2137X
Page 187: Loader for ADSP-2126x/2136x/2137x S
Page 191 and 192: Loader for ADSP-2126x/2136x/2137x S
Page 227 and 228: File Searches Loader for ADSP-2126x
Page 235 and 236: 6 LOADER FOR TIGERSHARC PROCESSORS
Page 237 and 238: � EE-174: Loader for TigerSHARC P
Page 239 and 240:
Boot Kernel Modification Loader for
Page 241 and 242:
Loader for TigerSHARC Processors el
Page 243 and 244:
TigerSHARC Command-Line Switches Lo
Page 245 and 246:
Loader for TigerSHARC Processors Ta
Page 247 and 248:
7 SPLITTER FOR SHARC AND TIGERSHARC
Page 249 and 250:
� Most Splitter for SHARC and Tig
Page 251 and 252:
Splitter for SHARC and TigerSHARC P
Page 253 and 254:
Page 255 and 256:
Page 257 and 258:
A FILE FORMATS VisualDSP++ developm
Page 259 and 260:
Assembly Source Files File Formats
Page 261 and 262:
Build Files File Formats Build file
Page 263 and 264:
Memory Map Files File Formats The l
Page 265 and 266:
Table A-4. End-of-File Record Examp
Page 267 and 268:
This example shows how to include t
Page 269 and 270:
Table A-7. S1 Termination Record Ex
Page 271 and 272:
File Formats A block of data record
Page 273 and 274:
Table A-9. SPORT Data File Example
Page 275 and 276:
B UTILITIES The VisualDSP++ develop
Page 277 and 278:
elf2flt - ELF to BFLT File Converte
Page 279 and 280:
Table B-3. BFLT File Dumper Command
Page 281 and 282:
I INDEX Numerics -64 splitter switc
Page 283 and 284:
BMS pins ADSP-2106x/160 processors,
Page 285 and 286:
data initialization files (.dat), A
Page 287 and 288:
external memory (SHARC processors)
Page 289 and 290:
initialization blocks (Blackfin pro
Page 291 and 292:
loader file formats (ADSP-BF535 pro
Page 293 and 294:
P -p # loader switch for Blackfin,
Page 295 and 296:
shared memory Blackfin processors,
Page 297 and 298:
V .VAR directive, A-3 vector addres
show all

VisualDSP++ 4.5 Loader and Utilities Manual - Analog Devices

You also want an ePaper? Increase the reach of your titles

Delete template?

Save as template?