VisualDSP++ 4.5 Loader and Utilities Manual - Analog Devices

ADSP-2106x/21160 Processor Booting
Table 3-10. Host Connections to ADSP-2106x/21160 Processors
Processor Connection/Data Bus Pins
ADSP-21060/61/62 Host connected to DATA47—16 or DATA31—16 pins (based on HPM
bits)
ADSP-21065L Host connected to DATA31—0 or DATA15—0 or DATA7—0 pins (based
on HBW bits)
ADSP-21160 Host connected to DATA63—32 or DATA47—31 pins (based on HPM
bits)
ADSP-21060/61/62/65L ADSP-21065L host address to IOP registers only
ADSP-21160 ADSP-21160 host address to IOP registers and internal memory
After reset, the processor goes into an idle stage with:
PC set to address 0x20004 on ADSP-21060/61/62 processors
PC set to address 0x8004 on ADSP-21065L processors
PC set to address 0x40004 on ADSP-21160 processors
The parameter registers for the external port DMA channel (0, 6, or 10)
are initialized as shown in Table 3-8 and Table 3-9, except that registers
EIx, EMx and ECx are not initialized and no DMA transfers start.
The DMA channel control register (DMAC6) for ADSP-21060/61/62 processors,
DMAC0 for ADSP-21065L processors, or DMAC10 for ADSP-21160
processors) is initialized, which allows external port DMA enable and
selects DTYPE for instruction words, PMODE for 16- to 48-bit word packing
(8- to 48-bit for ADSP-21065L processors), and least significant word
first.
Because the host processor is accessing the EPB0 external port buffer, the
HPM host packing mode bits of the SYSCON register must correspond to the
external bus width specified by the PMODE bits of DMACx control register.
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