VisualDSP++ 4.5 Loader and Utilities Manual - Analog Devices

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Blackfin Processor Booting Blackfin Processor Booting A Blackfin processor can be booted from an 8- or 16-bit flash/PROM memory or from an 8-,16-, or 24-bit addressable SPI memory. (The ADSP-BF561/BF566 processors does not support 24-bit addressable SPI memory boot.) There is also a no-boot option (bypass mode) in which execution occurs from a 16-bit external memory. At power-up, after a reset, the processor transitions into a boot mode sequence configured by the BMODE pins (Table 2-1). The BMODE pins are dedicated mode-control pins; that is, no other functions are performed by these pins. The pins can be read through bits in the system reset configuration register SYSCR (Figure 2-2). � Refer to the processor’s datasheet and hardware reference for more information on system configuration, peripherals, registers, and operating modes. ADSP-BF535 Processor Booting Upon reset, an ADSP-BF535 processor jumps to an external 16-bit memory for execution (if BMODE = 000) or to the on-chip boot ROM (if BMODE = 001, 010, or 011). Table 2-1 summarizes boot modes and code execution start addresses for ADSP-BF535 processors. Table 2-1. ADSP-BF535 Processor Boot Mode Selections Boot Source BMODE[2:0] Execution Start Address Execute from a 16-bit external memory (async bank 0); no-boot mode (bypass on-chip boot ROM); see on page 2-79. 000 0x2000 0000 Boot from an 8-bit/16-bit flash memory 001 0xF000 0000 1 Boot from an 8-bit address SPI0 serial EEPROM 010 0xF000 0000 1 2-2 VisualDSP++ 4.5 Loader and Utilities Manual
Loader/Splitter for Blackfin Processors Table 2-1. ADSP-BF535 Processor Boot Mode Selections (Cont’d) Boot Source BMODE[2:0] Execution Start Address Boot from a 16-bit address SPI0 serial EEPROM 011 0xF000 0000 1 Reserved 111—100 N/A 1 The processor jumps to this location after the booting is complete. A description of each boot mode is as follows. “ADSP-BF535 Processor On-Chip Boot ROM” on page 2-4 “ADSP-BF535 Processor Second-Stage Loader” on page 2-6 “ADSP-BF535 and ADSP-BF531/BF532/BF533/BF534/ BF536/BF537/BF538/BF539 Processor No-Boot Mode” on page 2-79 “ADSP-BF535 Processor Boot Streams” on page 2-8 “ADSP-BF535 Processor Memory Ranges” on page 2-14 VisualDSP++ 4.5 Loader and Utilities Manual 2-3
Page 1 and 2: Analog Devices, Inc. One Technology
Page 3 and 4: CONTENTS PREFACE Purpose of This Ma
Page 5 and 6: CONTENTS Loader Files Without a Sec
Page 7 and 8: CONTENTS ADSP-BF535 and ADSP-BF531/
Page 9 and 10: Contents File Extensions ..........
Page 11 and 12: Contents Boot Type Selection ......
Page 13 and 14: PREFACE Thank you for purchasing Vi
Page 15 and 16: Technical or Customer Support Prefa
Page 17 and 18: ADSP-21367 ADSP-21368 ADSP21369 ADS
Page 19 and 20: Preface VisualDSP++ 4.5 C/C++ Compi
Page 21 and 22: VisualDSP++ Documentation Set Prefa
Page 23 and 24: 1 INTRODUCTION The majority of this
Page 25 and 26: Loader Command Line Introduction If
Page 27 and 28: Initialization Code Introduction In
Page 29 and 30: A brief description of each phase f
Page 31 and 32: Introduction Download the loadable
Page 33 and 34: Introduction You can run the loader
Page 35 and 36: PROM Boot Mode Introduction After r
Page 37 and 38: Boot Streams Introduction The loade
Page 39: 2 LOADER/SPLITTER FOR BLACKFIN PROC
Page 43 and 44: System Reset Configuration Register
Page 45 and 46: Loader/Splitter for Blackfin Proces
Page 49 and 50: D7 OUTPUT .LDR FILE 4-BYTE HEADER F
Page 53 and 54: Second-Stage Loader Restrictions Lo
Page 63 and 64: SPI Memory Detection Routine Loader
Page 77 and 78: P0.H = HI(EBIU_SDRRC); R0 = 0x074A(
Page 79 and 80: � Booting � SDRAM ADSP-BF536 pr
Page 85 and 86: 1-0-Byte Block Header Block Data Lo
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Loader/Splitter for Blackfin Proces
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� The Core B Loader/Splitter for
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INITIALIZATION CODE (KERNEL WITH DE
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FLASH MEMORY INIT CODE HEADER INIT
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where: � Command-line File Search
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Blackfin Loader Command-Line Switch
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Using Base Loader Loader/Splitter f
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Table 2-11. Base Load Page Settings
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Using Second-Stage Loader Loader/Sp
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3 LOADER FOR ADSP-2106X/21160 SHARC
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Loader for ADSP-2106x/21160 SHARC P
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Boot Mode Selection Loader for ADSP
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File Searches Loader for ADSP-2106x
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-si-revision #|none|any Loader for
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4 LOADER FOR ADSP-21161 SHARC PROCE
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Loader for ADSP-21161 SHARC Process
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ADSP-21161 Processor Boot Streams L
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To Modify a Boot Kernel Source File
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Processor ID Numbers Loader for ADS
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File Searches Loader for ADSP-21161
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5 LOADER FOR ADSP-2126X/2136X/2137X
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Loader for ADSP-2126x/2136x/2137x S
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File Searches Loader for ADSP-2126x
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6 LOADER FOR TIGERSHARC PROCESSORS
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� EE-174: Loader for TigerSHARC P
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Boot Kernel Modification Loader for
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Loader for TigerSHARC Processors el
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TigerSHARC Command-Line Switches Lo
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Loader for TigerSHARC Processors Ta
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7 SPLITTER FOR SHARC AND TIGERSHARC
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� Most Splitter for SHARC and Tig
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Splitter for SHARC and TigerSHARC P
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A FILE FORMATS VisualDSP++ developm
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Assembly Source Files File Formats
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Build Files File Formats Build file
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Memory Map Files File Formats The l
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Table A-4. End-of-File Record Examp
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This example shows how to include t
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Table A-7. S1 Termination Record Ex
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File Formats A block of data record
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Table A-9. SPORT Data File Example
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B UTILITIES The VisualDSP++ develop
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elf2flt - ELF to BFLT File Converte
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Table B-3. BFLT File Dumper Command
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I INDEX Numerics -64 splitter switc
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BMS pins ADSP-2106x/160 processors,
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data initialization files (.dat), A
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external memory (SHARC processors)
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initialization blocks (Blackfin pro
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loader file formats (ADSP-BF535 pro
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P -p # loader switch for Blackfin,
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shared memory Blackfin processors,
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V .VAR directive, A-3 vector addres
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VisualDSP++ 4.5 Loader and Utilities Manual - Analog Devices

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