VisualDSP++ 4.5 Loader and Utilities Manual - Analog Devices

ADSP-21161 Processor Booting
After the boot process loads 256 words into memory locations 0x40000
through 0x400FF, the processor begins executing instructions. Because
most processor programs require more than 256 words of instructions and
initialization data, the 256 words typically serve as a loading routine for
the application. VisualDSP++ includes loading routines (boot kernels)
that can load entire programs; refer to “ADSP-21161 Processor Boot Kernels”
on page 4-16 for more information.
Refer to the ADSP-21161 SHARC DSP Hardware Reference for detailed
information on DMA and system configurations.
� DMA
channel differences between ADSP-21161 and previous
SHARC family processors (ADSP-2106x) account for boot differences.
Even with these differences, ADSP-21161 processors
support the same boot capability and configuration as
ADSP-2106x processors. The DMAC10 register default values differ
because the ADSP-21161processor has additional parameters and
different DMA channel assignments. Host boot mode uses EPB0,
DMA channel 10.
The processor determines the boot mode at reset from the EBOOT, LBOOT,
and BMS pin inputs. When EBOOT=0, LBOOT=0, and BMS=1, the processor
boots from a host through the external port. Refer to Table 4-1 and
Table 4-2 on page 4-4 for boot mode selection.
When using any of the power-up boot modes, address 0x40004 should not
contain a valid instruction. Because it is not executed during the boot
sequence, place a NOP or IDLE instruction at this location.
During reset, the processor ACK line is internally pulled high with an
equivalent 20K ohm resistor and is held high with an internal keeper
latch. It is not necessary to use an external pull-up resistor on the ACK line
during booting or at any other time.
4-10 VisualDSP++ 4.5 Loader and Utilities Manual