VisualDSP++ 4.5 Loader and Utilities Manual - Analog Devices

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Blackfin Processor Booting Load bytes into L1 instruction memory by using the instruction test command and data registers, as described in the Memory chapter of the appropriate hardware reference manual. These registers transfer 8-byte sections of data from external memory to internal L1 instruction memory. ADSP-BF531/BF532/BF533/BF534/BF536/BF537/ BF538/BF539 Processor Booting Upon reset, an ADSP-BF531/BF532/BF533/BF534/BF536/BF537/ BF538/BF539 processor jumps to the on-chip boot ROM or jumps to 16-bit external memory for execution (if BMODE = 0) located at 0xEF00 0000. Table 2-2 shows boot modes and execution start addresses for ADSP-BF531, ADSP-BF532, ADSP-BF533, ADSP-BF538, and ADSP-BF539 processors. Table 2-3 shows boot modes for ADSP-BF534/BF536/BF537 processors, which in addition to all ADSP-BF531/BF532/BF533 processor boot modes, also can boot from a TWI serial device, a TWI host, and a UART host. 2-16 VisualDSP++ 4.5 Loader and Utilities Manual
Loader/Splitter for Blackfin Processors Table 2-2. Processor Boot Mode Selections for ADSP-BF531/BF532/ BF533/BF538/BF539 Processors Boot Source BMODE[1:0] Execute from 16-bit External ASYNC bank 0 memory (no-boot mode or bypass on-chip boot ROM); see on page 2-79 Execution Start Address ADSP-BF531 ADSP-BF532 ADSP-BF538 ADSP-BF533 ADSP-BF539 00 0x2000 0000 0x2000 0000 Boot from 8- or 16-bit PROM/flash 01 0xFFA0 8000 0xFFA0 0000 Boot from an SPI host in SPI slave mode 10 0xFFA0 8000 0xFFA0 0000 Boot from an 8-, 16-, or 24-bit addressable SPI memory in SPI master boot mode with support for Atmel AT45DB041B, AT45DB081B, and AT45DB161B DataFlash devices 11 0xFFA0 8000 0xFFA0 0000 Table 2-3. ADSP-BF534/BF536/BF537 Processor Boot Modes Boot Source BMODE[2:0] Executes from external 16-bit memory connected to ASYNC bank 0; (no-boot mode or bypass on-chip boot ROM); see on page 2-79 VisualDSP++ 4.5 Loader and Utilities Manual 2-17 000 Boots from 8/16-bit PROM/flash 001 Reserved 010 Boots from an 8-, 16-, or 24-bit addressable SPI memory in SPI master mode with support for Atmel AT45DB041B, AT45DB081B, and AT45DB161B DataFlash devices 011 Boots from an SPI host in SPI slave mode 100 Boots from a TWI serial device 101 Boots from a TWI host 110 Boots from a UART host 111
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Analog Devices, Inc. One Technology
Page 3 and 4: CONTENTS PREFACE Purpose of This Ma
Page 5 and 6: CONTENTS Loader Files Without a Sec
Page 7 and 8: CONTENTS ADSP-BF535 and ADSP-BF531/
Page 9 and 10: Contents File Extensions ..........
Page 11 and 12: Contents Boot Type Selection ......
Page 13 and 14: PREFACE Thank you for purchasing Vi
Page 15 and 16: Technical or Customer Support Prefa
Page 17 and 18: ADSP-21367 ADSP-21368 ADSP21369 ADS
Page 19 and 20: Preface VisualDSP++ 4.5 C/C++ Compi
Page 21 and 22: VisualDSP++ Documentation Set Prefa
Page 23 and 24: 1 INTRODUCTION The majority of this
Page 25 and 26: Loader Command Line Introduction If
Page 27 and 28: Initialization Code Introduction In
Page 29 and 30: A brief description of each phase f
Page 31 and 32: Introduction Download the loadable
Page 33 and 34: Introduction You can run the loader
Page 35 and 36: PROM Boot Mode Introduction After r
Page 37 and 38: Boot Streams Introduction The loade
Page 39 and 40: 2 LOADER/SPLITTER FOR BLACKFIN PROC
Page 41 and 42: Loader/Splitter for Blackfin Proces
Page 43 and 44: System Reset Configuration Register
Page 49 and 50: D7 OUTPUT .LDR FILE 4-BYTE HEADER F
Page 53: Second-Stage Loader Restrictions Lo
Page 63 and 64: SPI Memory Detection Routine Loader
Page 77 and 78: P0.H = HI(EBIU_SDRRC); R0 = 0x074A(
Page 79 and 80: � Booting � SDRAM ADSP-BF536 pr
Page 85 and 86: 1-0-Byte Block Header Block Data Lo
Page 93 and 94: � The Core B Loader/Splitter for
Page 95 and 96: INITIALIZATION CODE (KERNEL WITH DE
Page 99 and 100: FLASH MEMORY INIT CODE HEADER INIT
Page 101 and 102: where: � Command-line File Search
Page 103 and 104: Blackfin Loader Command-Line Switch
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Loader/Splitter for Blackfin Proces
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Using Base Loader Loader/Splitter f
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Table 2-11. Base Load Page Settings
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Using Second-Stage Loader Loader/Sp
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3 LOADER FOR ADSP-2106X/21160 SHARC
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Loader for ADSP-2106x/21160 SHARC P
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Boot Mode Selection Loader for ADSP
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File Searches Loader for ADSP-2106x
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-si-revision #|none|any Loader for
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4 LOADER FOR ADSP-21161 SHARC PROCE
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Loader for ADSP-21161 SHARC Process
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ADSP-21161 Processor Boot Streams L
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To Modify a Boot Kernel Source File
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Processor ID Numbers Loader for ADS
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File Searches Loader for ADSP-21161
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5 LOADER FOR ADSP-2126X/2136X/2137X
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Loader for ADSP-2126x/2136x/2137x S
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File Searches Loader for ADSP-2126x
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6 LOADER FOR TIGERSHARC PROCESSORS
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� EE-174: Loader for TigerSHARC P
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Boot Kernel Modification Loader for
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Loader for TigerSHARC Processors el
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TigerSHARC Command-Line Switches Lo
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Loader for TigerSHARC Processors Ta
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7 SPLITTER FOR SHARC AND TIGERSHARC
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� Most Splitter for SHARC and Tig
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Splitter for SHARC and TigerSHARC P
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A FILE FORMATS VisualDSP++ developm
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Assembly Source Files File Formats
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Build Files File Formats Build file
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Memory Map Files File Formats The l
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Table A-4. End-of-File Record Examp
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This example shows how to include t
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Table A-7. S1 Termination Record Ex
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File Formats A block of data record
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Table A-9. SPORT Data File Example
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B UTILITIES The VisualDSP++ develop
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elf2flt - ELF to BFLT File Converte
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Table B-3. BFLT File Dumper Command
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I INDEX Numerics -64 splitter switc
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BMS pins ADSP-2106x/160 processors,
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data initialization files (.dat), A
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external memory (SHARC processors)
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initialization blocks (Blackfin pro
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loader file formats (ADSP-BF535 pro
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P -p # loader switch for Blackfin,
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shared memory Blackfin processors,
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V .VAR directive, A-3 vector addres
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VisualDSP++ 4.5 Loader and Utilities Manual - Analog Devices

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