VisualDSP++ 4.5 Loader and Utilities Manual - Analog Devices

Second-Stage Loader Restrictions
Loader/Splitter for Blackfin Processors
Using the second-stage loader imposes the following restrictions.
� The
The bottom of L2 memory must be reserved during booting. These
locations can be reallocated during runtime. The following locations
pertain to the current second-stage loaders.
� For 8- and 16-bit PROM/flash booting, reserve
0xF003 FE00—0xF003 FFFF (last 512 bytes).
� For 8- and 16-bit addressable SPI booting, reserve
0xF003 FD00—0xF003 FFFF (last 768 bytes).
If segments reside in SDRAM memory, configure the SDRAM registers
accordingly in the second-stage loader before booting.
� Modify a section of code called “SDRAM setup” in the
second-stage loader and rebuild the second-stage loader.
Any segments residing in L1 instruction memory
(0xFFA0 0000–0xFFA0 3FFF) must be 8-byte aligned.
� Declare segments, within the .ldf file, that reside in L1
instruction memory at starting locations that are 8-byte
aligned (for example, 0xFFA0 0000, 0xFFA0 0008,
0xFFA0 0010, and so on).
� Use the .ALIGN 8; directives in the application code.
two reasons for these restrictions are:
Core writes into L1 instruction memory are not allowed.
DMA from an 8-bit external memory is not possible since
the minimum width of the external bus interface unit
(EBIU) is 16 bits.
VisualDSP++ 4.5 Loader and Utilities Manual 2-15