VisualDSP++ 4.5 Loader and Utilities Manual - Analog Devices

ADSP-2126x/2136x/2137x Processor Booting
Packing and Padding Details
For ZERO_INIT sections in a .dxe file, no data packing or padding in the
.ldr file is required because only the header itself is included in the .ldr
file. However, for other section types, additional data manipulation is
required. It is important to note that in all cases, the word count placed
into the block header in the loader file is the original number of words.
That is, the word count does not include the padded word.
SPI Port Boot Modes
The ADSP-2126x/2136x/2137x SHARC processor supports booting from
a host processor via serial peripheral interface slave mode (BOOT_CFG1–0 =
00), and booting from an SPI flash, SPI PROM, or a host processor via
SPI master mode (BOOT_CFG1–0 = 01). SPI slave boot mode is discussed
on page 5-9, and SPI master boot modes are discussed on page 5-10.
Both SPI boot modes support booting from 8-, 16-, or 32-bit SPI devices.
In all SPI boot modes, the data word size in the shift register is hardwired
to 32 bits. Therefore, for 8- or 16-bit devices, data words are packed into
the shift register (RXSPI) to generate 32-bit words least significant bit
(LSB) first, which are then shifted into internal memory.
For 16-bit SPI devices, two words shift into the 32-bit receive shift register
(RXSR) before a DMA transfer to internal memory occurs. For 8-bit SPI
devices, four words shift into the 32-bit receive shift register before a
DMA transfer to internal memory occurs.
When booting, the ADSP-2126x/2136x/2137x processor expects to
receive words into the RXSPI register seamlessly. This means that bits are
received continuously without breaks in the CS link. For different SPI host
sizes, the processor expects to receive instructions and data packed in a
least significant word (LSW) format.
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