VisualDSP++ 4.5 Loader and Utilities Manual - Analog Devices

SPI Memory Detection Routine
Loader/Splitter for Blackfin Processors
Since BMODE = 11 supports booting from various SPI memories, the
on-chip boot ROM detects what type of memory is connected. To determine
the type of memory connected to the processor (8-, 16-, or 24-bit
addressable), the on-chip boot ROM sends the following sequence of
bytes to the SPI memory until the memory responds back. The SPI memory
does not respond back until it is properly addressed. The on-chip boot
ROM does the following.
1. Sends the read command, 0x03, on the MOS1 pin, then does a
dummy read of the MISO pin.
2. Sends an address byte, 0x00, on the MOSI pin, then does a dummy
read of the MISO pin.
3. Sends another byte, 0x00, on the MOSI pin and checks whether the
incoming byte on the MISO pin is anything other than 0xFF (this is
the value from the pull-up resistor. For more information, refer to
the following note.) An incoming byte that is not 0xFF means that
the SPI memory has responded back after one address byte, and an
8-bit addressable SPI memory device is assumed to be connected.
4. If the incoming byte is 0xFF, the on-chip boot ROM sends another
byte, 0x00, on the MOSI pin and checks whether the incoming byte
on the MISO pin is anything other than 0xFF. An incoming byte
other than 0xFF means that the SPI memory has responded back
after two address bytes, and a 16-bit addressable SPI memory
device is assumed to be connected.
5. If the incoming byte is 0xFF, the on-chip boot ROM sends another
byte, 0x00, on the MOSI pin and checks whether the incoming byte
on the MISO pin is anything other than 0xFF. An incoming byte
other than 0xFF means that the SPI memory has responded back
after three address bytes, and a 24-bit addressable SPI memory
device is assumed to be connected.
VisualDSP++ 4.5 Loader and Utilities Manual 2-25