VisualDSP++ 4.5 Loader and Utilities Manual - Analog Devices

initialization blocks (Blackfin processors)
ADSP-BF531/2/3/4/6/7/8/9 processors,
2-21, 2-35, 2-36, 2-53
ADSP-BF561/6 processors, 2-49, 2-50,
2-53
code example, 2-38, 2-53
initial word option (SHARC processors),
5-14, 5-15
INIT_L16 blocks, 5-27
INIT_L48 blocks, 5-26
INIT_L64 blocks, 5-28
input file formats, See source file formats
input files
executable (.dxe) files, 2-64, 3-26, 4-25,
5-42, 6-8
extracting memory sections from, 7-5,
7-6
in multiprocessor systems, 6-6
instruction SRAM (Blackfin processors)
ADSP-BF531/2/3/4/6/7/8/9 processors,
2-40
ADSP-BF535 processors, 2-14
ADSP-BF561/6 processors, 2-50, 2-54
Intel hex-32 file format, 2-66, 6-9, A-7
internal boot mode (SHARC processors),
5-17
internal memory, boot-loadable file
execution, 1-9
internal vector tables, 3-22, 4-21
interrupt vector location, 4-9, 4-12
interrupt vector tables, 3-22, 4-21, 5-17,
5-18, 5-22, 5-29, 5-30
IOP registers, 3-12, 3-13
IRQ vector, 3-8, 3-9
INDEX
IVG15 lowest priority interrupt, 2-4, 2-19,
2-35, 2-43
K
-kb
prom|flash|spi|spislave|UART|TWI|F
IFO, loader switch for Blackfin, 2-67
-kenc dll_filename, loader switch for
Blackfin, 2-68
Kernel (Load) page (Blackfin processors),
2-77
kernels (ADSP-2106x/160 processors)
boot sequence, 3-3, 3-16
default source files, 3-16, 3-21
loading to processor, 3-10, 3-13
modifying, 3-19
rebuilding, 3-22
replacing with application code, 3-18
specifying user kernel, 3-30
kernels (ADSP-21161 processors)
boot sequence, 4-3
default source files, 4-16, 4-19
modifying, 4-18, 4-19
rebuilding, 4-18, 4-19
kernels (ADSP-2126x/36x/37x processors)
boot sequence, 5-3, 5-19
compression/decompression, 5-35, 5-36,
5-40
default source files, 5-19
loading to processor, 5-9, 5-13
modifying, 5-20
omitting in output, 5-17
rebuilding, 5-20, 5-21
VisualDSP++ 4.5 Loader and Utilities Manual I-9