VisualDSP++ 4.5 Loader and Utilities Manual - Analog Devices

ADSP-21161 Processor Booting
Refer to the ADSP-21161 SHARC DSP Hardware Reference for detailed
information on DMA and system configurations.
� Be
aware that DMA channel differences between the ADSP-21161
and previous SHARC processors (ADSP-2106x) account for boot
differences. Even with these differences, the ADSP-21161 processor
supports the same boot capability and configuration as the
ADSP-2106x processors. The DMACx register default values differ
because the ADSP-21161 processor has additional parameters and
different DMA channel assignments. EPROM boot mode uses
EPB0, DMA channel 10. Similar to ADSP-2106x processors, the
ADSP-21161processor boots from DATA23—16.
The processor determines the booting mode at reset from the EBOOT,
LBOOT, and BMS pin inputs. When EBOOT=1 and LBOOT=0, the processor
boots from an EPROM through the external port and uses BMS as the
memory select output. For information on boot mode selection, see the
boot memory select pin descriptions in Table 4-1 and Table 4-2 on
page 4-4.
� When
using any of the power-up boot modes, address 0x40004
should not contain a valid instruction since it is not executed during
the booting sequence. Place a NOP or IDLE instruction at this
location.
EPROM boot (boot space 8M x 8-bit) through the external port requires
that an 8-bit wide boot EPROM be connected to the processor data bus
pins 23–16 (DATA23—16). The processor’s lowest address pins should be
connected to the EPROM address lines. The EPROM’s chip select should
be connected to BMS, and its output enable should be connected to RD.
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