VisualDSP++ 4.5 Loader and Utilities Manual - Analog Devices

ADSP-2126x/2136x/2137x Processor Booting
From the perspective of the processor, there is no difference between booting
from the three types of SPI slave devices. Since SPI is a full-duplex
protocol, the processor is receiving the same amount of bits that it sends as
a read command. The read command comprises a full 32-bit word (which
is what the processor is initialized to send) comprised of a 24-bit address
with an 8-bit opcode. The 32-bit word, received while the read command
is transmitted, is thrown away in hardware and can never be recovered by
the user. Consequently, special measures must be taken to guarantee that
the boot stream is identical in all three cases.
The processor boots in least significant bit first (LSB) format, while most
serial memory devices operate in most significant bit first (MSB) format.
Therefore, it is necessary to program the device in a fashion that is compatible
with the required LSB format. See “Bit-Reverse Option for SPI
Boot Modes” on page 5-13 for details.
Also, because the processor always transmits 32 bits before it begins reading
boot data from the slave device, the loader utility must insert extra
data into the byte stream (in the loader file) if using memory devices that
do not use the LSB format. The loader utility includes an option for creating
a boot stream compatible with both endian formats, and devices
requiring 16-bit and 24-bit addresses, as well as those requiring no read
command at all. See “Initial Word Option for SPI Master Boot Modes”
on page 5-14 for details.
Figure 5-1 shows the initial 32-bit word sent out from the processor. As
shown in the figure, the processor initiates the SPI master boot process by
writing an 8-bit opcode (LSB first) to the slave device to specify a read
operation. This read opcode is fixed to 0xC0 (0x03 in MSB first format).
Following that, a 24-bit address (all zeros) is always driven by the proces-
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