VisualDSP++ 4.5 Loader and Utilities Manual - Analog Devices

INDEX
SPISS pin, 2-22
Split page, 7-9
splitter
introduction to, 1-8, 1-9, 1-11, 1-12
as ROM splitter on Blackfin processors,
2-74
command-line syntax, 7-2
file extensions, 7-4
graphical user interface, 7-9
list of switches, 7-5
output file formats, A-11, A-13, A-14,
A-15
SPORT hex data files, A-16
SRAM memory (Blackfin processors)
ADSP-BF531/2/3/4/6/7/8/9 processors,
2-40
ADSP-BF535 processors, 2-14
ADSP-BF561/6 processors, 2-42, 2-54
-s section_name, splitter switch, 7-6
start addresses
ADSP-2106x/160 application code, 3-4
Blackfin application code, 2-70, 2-74
status information, 2-72, 2-74
.stk (byte-stacked) files, 7-4, 7-6, 7-7, A-14
streams, See boot streams
supervisor mode (Blackfin processors)
ADSP-BF531/2/3/4/6/7/8/9 processors,
2-19
ADSP-BF535 processors, 2-4
ADSP-BF561/6 processors, 2-43
synchronous boot operations, 3-13
SYSCON register (SHARC processors)
ADSP-2106x/160 processors, 3-10,
3-12, 3-13, 3-19, 3-22
ADSP-21161 processors, 4-18, 4-21
ADSP-2126x/36x/37x processors, 5-20,
5-22
SYSCR register (Blackfin processors)
ADSP-BF531/2/3/4/6/7/8/9 processors,
2-19
ADSP-BF535 processors, 2-5
ADSP-BF561/6 processors, 2-43, 2-44
SYSCTL register, 5-31
SYSTAT register, 3-23
system clock frequency (ADSP-BF533
EZ-KIT Lite), 2-26
system reset configuration register, See
SYSCR register, 2-4
T
-t#
loader switch for SHARC, 3-31, 4-31
loader switch for TigerSHARC, 6-10
termination records, A-12, A-13
text files, 2-21, A-4, A-15
TigerSHARC processors, boot modes, 6-2,
6-3, 6-9
timeout cycles (TigerSHARC processors),
6-10
two-wire interface (TWI) boot mode
ADSP-BF534/6/7 processors, 2-17,
2-27, 2-29, 2-35
.txt (ASCII text) files, A-4
U
-u, splitter switch, 7-7
UART slave boot mode (Blackfin
processors), 2-17, 2-30
UBWM register, 3-11
uncompressed streams, 2-59, 5-39
-use32bit Tags for External Memory
Blocks, loader switch for SHARC,
3-31
utility programs, B-2
I-16 VisualDSP++ 4.5 Loader and Utilities Manual