VisualDSP++ 4.5 Loader and Utilities Manual - Analog Devices

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ADSP-21161 Processor Booting Table 4-5. DMA Channel 8 Parameter Register for Link Port Boot Parameter Register Initialization Value IILB0 0x0004 0000 IMLB0 Uninitialized (increment by 1 is automatic) CLB0 0x0100 (256-instruction words) CPLB0 Uninitialized GPLB0 Uninitialized In systems where multiple processors are not connected by the parallel external bus, booting can be accomplished from a single source through the link ports. To simultaneously boot all the processors, make a parallel common connection to link buffer 0 on each of the processors. If a daisy chain connection exists between the processors’ link ports, each processor can boot the next processor in turn. Link buffer 0 must always be used for booting. SPI Port Boot Mode Serial peripheral interface (SPI) port booting uses DMA channel 8 of the IO processor to transfer instructions to internal memory. In this boot mode, the processor receives 8-bit wide data in the SPIRx register. During the boot process, the program loads 256 words into memory locations 0x40000 through 0x400FF. The processor subsequently begins executing instructions. Because most processor programs require more than 256 words of instructions and initialization data, the 256 words typically serve as a loading routine for the application. VisualDSP++ includes loading routines (boot kernels) which load an entire program through the selected port. See “ADSP-21161 Processor Boot Kernels” on page 4-16 for more information. 4-14 VisualDSP++ 4.5 Loader and Utilities Manual
Loader for ADSP-21161 SHARC Processors Refer to the ADSP-21161 SHARC DSP Hardware Reference for detailed information on DMA and system configurations. For information about SPI slave booting, refer to EE-177: SHARC SPI Booting, located on the Analog Devices processor Web site. The processor determines the boot mode at reset from the EBOOT, LBOOT, and BMS pin inputs. When EBOOT=0, LBOOT=1, and BMS=0, the processor boots through its SPI port. For information on the boot mode selection, see Table 4-1 and Table 4-2 on page 4-4. � When using any of the power-up booting modes, address 0x40004 should not contain a valid instruction. Because it is not executed during the boot sequence, place a NOP or IDLE instruction placed at this location. For SPI port boot, the processor gets boot data after system power-up from another processor’s SPI port or another SPI compatible device. Table 4-6 shows how the DMA channel 8 parameter registers are initialized at reset. The SPI control register (SPICTL) is configured to 0x0A001F81 upon reset during SPI boot. This configuration sets up the SPIRx register for 32-bit serial transfers. The SPIRx DMA channel 8 parameter registers are configured to DMA in 0x180 32-bit words into internal memory normal word address space starting at 0x40000. Once the 32-bit DMA transfer completes, the data is accessed as 3 column, 48-bit instructions. The processor executes a 256 word (0x100) boot kernel upon completion of the 32-bit, 0x180 word DMA. For 16-bit SPI hosts, two words are shifted into the 32-bit receive shift register before a DMA transfer to internal memory occurs. For 8-bit SPI hosts, four words are shifted into the 32-bit receive shift register before a DMA transfer to internal memory occurs. VisualDSP++ 4.5 Loader and Utilities Manual 4-15
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Analog Devices, Inc. One Technology
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CONTENTS PREFACE Purpose of This Ma
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CONTENTS Loader Files Without a Sec
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CONTENTS ADSP-BF535 and ADSP-BF531/
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Contents File Extensions ..........
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Contents Boot Type Selection ......
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PREFACE Thank you for purchasing Vi
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Technical or Customer Support Prefa
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ADSP-21367 ADSP-21368 ADSP21369 ADS
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Preface VisualDSP++ 4.5 C/C++ Compi
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VisualDSP++ Documentation Set Prefa
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1 INTRODUCTION The majority of this
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Loader Command Line Introduction If
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Initialization Code Introduction In
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A brief description of each phase f
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Introduction Download the loadable
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Introduction You can run the loader
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PROM Boot Mode Introduction After r
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Boot Streams Introduction The loade
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2 LOADER/SPLITTER FOR BLACKFIN PROC
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Loader/Splitter for Blackfin Proces
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System Reset Configuration Register
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D7 OUTPUT .LDR FILE 4-BYTE HEADER F
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Second-Stage Loader Restrictions Lo
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SPI Memory Detection Routine Loader
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P0.H = HI(EBIU_SDRRC); R0 = 0x074A(
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� Booting � SDRAM ADSP-BF536 pr
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1-0-Byte Block Header Block Data Lo
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� The Core B Loader/Splitter for
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INITIALIZATION CODE (KERNEL WITH DE
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FLASH MEMORY INIT CODE HEADER INIT
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where: � Command-line File Search
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Blackfin Loader Command-Line Switch
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Using Base Loader Loader/Splitter f
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Table 2-11. Base Load Page Settings
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Page 121 and 122: 3 LOADER FOR ADSP-2106X/21160 SHARC
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Page 125 and 126: Boot Mode Selection Loader for ADSP
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Page 153 and 154: 4 LOADER FOR ADSP-21161 SHARC PROCE
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Page 165: Loader for ADSP-21161 SHARC Process
Page 169 and 170: ADSP-21161 Processor Boot Streams L
Page 171 and 172: To Modify a Boot Kernel Source File
Page 175 and 176: Processor ID Numbers Loader for ADS
Page 179 and 180: File Searches Loader for ADSP-21161
Page 185 and 186: 5 LOADER FOR ADSP-2126X/2136X/2137X
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Loader for ADSP-2126x/2136x/2137x S
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File Searches Loader for ADSP-2126x
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6 LOADER FOR TIGERSHARC PROCESSORS
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� EE-174: Loader for TigerSHARC P
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Boot Kernel Modification Loader for
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Loader for TigerSHARC Processors el
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TigerSHARC Command-Line Switches Lo
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Loader for TigerSHARC Processors Ta
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7 SPLITTER FOR SHARC AND TIGERSHARC
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� Most Splitter for SHARC and Tig
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Splitter for SHARC and TigerSHARC P
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A FILE FORMATS VisualDSP++ developm
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Assembly Source Files File Formats
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Build Files File Formats Build file
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Memory Map Files File Formats The l
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Table A-4. End-of-File Record Examp
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This example shows how to include t
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Table A-7. S1 Termination Record Ex
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File Formats A block of data record
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Table A-9. SPORT Data File Example
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B UTILITIES The VisualDSP++ develop
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elf2flt - ELF to BFLT File Converte
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Table B-3. BFLT File Dumper Command
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I INDEX Numerics -64 splitter switc
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BMS pins ADSP-2106x/160 processors,
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data initialization files (.dat), A
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external memory (SHARC processors)
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initialization blocks (Blackfin pro
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loader file formats (ADSP-BF535 pro
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P -p # loader switch for Blackfin,
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shared memory Blackfin processors,
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V .VAR directive, A-3 vector addres
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VisualDSP++ 4.5 Loader and Utilities Manual - Analog Devices

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