VisualDSP++ 4.5 Loader and Utilities Manual - Analog Devices

� The
Core B
Loader/Splitter for Blackfin Processors
� L1 instruction SRAM (0xFF60 0000 – 0xFF6 03FFF)
� L1 instruction cache/SRAM (0xFF61 0000 – 0xFF61 3FFF)
� L1 data bank A SRAM (0xFF40 0000 – 0xFF40 3FFF)
� L1 data bank A cache/SRAM (0xFF40 4000 – 0xFF40 7FFF)
� L1 data bank B SRAM (0xFF50 0000 – 0xFF50 3FFF)
� L1 data bank B cache/SRAM (0xFF50 4000 – 0xFF50 7FFF)
128K of shared L2 memory (FEB0 0000 – FEB1 FFFF)
Four banks of configurable synchronous DRAM
(0x0000 0000 –(upto)0x1FFF FFFF)
boot ROM does not support booting to core A scratch memory
(0xFFB0 0000 – 0xFFB0 0FFF) and to core B scratch memory
(0xFF70 0000–0xFF70 0FFF). Data that needs to be initialized prior
to runtime should not be placed in scratch memory.
ADSP-BF531/BF532/BF533/BF534/BF536/BF537
Processor Compression Support
The loader utility for ADSP-BF531/BF532/BF533/BF534/BF536/BF537
processors offers a loader file (boot stream) compression mechanism
known as zLib. The zLib compression is supported by a third party
dynamic link library, zLib1.dll. Additional information about the library
can be obtained from the http://www.zlib.net Web site.
The zLib1.dll dynamic link library is included in VisualDSP++. The
library functions perform the boot stream compression and decompression
procedures when the appropriate options are selected for the loader utility.
The initialization executable files with built-in decompression mechanism
VisualDSP++ 4.5 Loader and Utilities Manual 2-55