VisualDSP++ 4.5 Loader and Utilities Manual - Analog Devices

Blackfin Processor Booting
� On
the Blackfin processor, in both TWI master and slave boot
modes, the upper 256 bytes of data bank A starting at address
0xFF90 3F00 must not be used. The boot ROM code uses this
space for the TWI boot modes to temporarily hold the serial data
which is then transferred to L1 instruction memory using DMA.
ADSP-BF534/BF536/BF537 UART Slave Mode Boot via
Master Host (BMODE = 111)
UART booting on the Blackfin processor is supported only through
UART0, and the Blackfin processor is always a slave.
Using an autobaud detection sequence, a boot-stream-formatted program
is downloaded by the host. The host agent selects a bit rate within the
UART’s clocking capabilities. When performing the autobaud, the UART
expects an “@” character (0x40, eight bits data, one start bit, one stop bit,
no parity bit) on the UART0 RXD input to determine the bit rate. The
hardware support and the mathematical operations to perform for this
autobaud detection is explained in Chapter 15, “General-Purpose Timers”
of the ADSP-BF537 Blackfin Processor Hardware Reference. The boot kernel
then replies with an acknowledgement, and then the host can
download the boot stream. The acknowledgement consists of the following
four bytes: 0xBF, UART0_DLL, UART0_DLH, 0x00. The host is requested
not to send further bytes until it has received the complete acknowledge
string. Once the 0x00 byte is received, the host can send the entire boot
stream at once. The host must know the total byte count of the boot
stream, but the host does not require any knowledge about the content of
the boot stream.
When the boot kernel is processing ZEROFILL or INIT blocks, it may
require extra processing time and needs to hold the host off from sending
more data. This is signalled with the HWAIT output which can operate on
any GPIO of port G. The GPIO, which is actually used, is encoded in the
FLAG word of all block headers. The boot kernel is not permitted to drive
any of the GPIOs before the first block header has been received and eval-
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