VisualDSP++ 4.5 Loader and Utilities Manual - Analog Devices

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ADSP-2106x/21160 Processor Booting Table 3-5. ADSP-21065L Boot Mode Pins Pin Type Description BMS I/O/T 1 Boot memory select When BSEL is low, BMS is an input pin and selects between host boot mode and no-boot mode. In no-boot mode, the processor executes from external memory. For no-boot mode, connect BMS to ground. For host boot mode, connect BMS to VDD. When BSEL is high, BMS is an output pin and the processor starts up in EPROM boot mode. Connect BMS to the EPROM’s chip select. BSEL I EPROM boot select Hardwire this signal; it is used for system configuration. When BSEL is high, the processor starts up in EPROM boot mode. The processor assumes the EPROM data bus is 8 bits wide. Connect BSEL to the processor data bus in LSB alignment. When BSEL is low, BMS determines the booting mode. Connect BSEL to ground. 1 Three-statable in EPROM boot mode (when BMS is an output). Table 3-6. ADSP-21065L Boot Modes BSEL BMS Description 0 1 No-boot mode. The processor executes from external memory at location 0x20004. 0 1 Host boot mode. The processor defaults to an 8-bit host bus width. 1 Output EPROM boot mode. The processor assumes an 8-bit EPROM data bus width. Connect to the data bus in LSB alignment. 3-6 VisualDSP++ 4.5 Loader and Utilities Manual
Loader for ADSP-2106x/21160 SHARC Processors ADSP-2106x/21160 Boot Modes ADSP-2106x/21160 processors support these boot modes: EPROM, host, and link. The following sections describe each of the modes. “EPROM Boot Mode” on page 3-7 “Host Boot Mode” on page 3-11 “Link Port Boot Mode” on page 3-15 “No-Boot Mode” on page 3-16 For multiprocessor booting, refer to “ADSP-2106x/21160 Multi-Application (Multi-DXE) Management” on page 3-23. EPROM Boot Mode The ADSP-2106x/21160 processor is configured for EPROM boot through the external port when the EBOOT pin is high and the LBOOT pin is low. These settings cause the BMS pin to become an output, serving as chip select for the EPROM. Table 3-7 lists all PROM-to-processor connections. Table 3-7. PROM Connections to ADSP-2106x/21160 Processors Processor Connection ADSP-21060/61/62 PROM/EPROM connects to DATA23—16 pins ADSP-21065L PROM/EPROM connects to DATA7—0 pins ADSP-21160 PROM/EPROM connects to DATA39—32 pins ADSP-21xxx Address pins of PROM connect to lowest address pins of any processor ADSP-21xxx Chip select connects to the BMS pin ADSP-21060/61/62/65L Output enable connects to the RD pin ADSP-21160 Output enable connects to RDH pin VisualDSP++ 4.5 Loader and Utilities Manual 3-7
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Analog Devices, Inc. One Technology
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CONTENTS PREFACE Purpose of This Ma
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CONTENTS Loader Files Without a Sec
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CONTENTS ADSP-BF535 and ADSP-BF531/
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Contents File Extensions ..........
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Contents Boot Type Selection ......
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PREFACE Thank you for purchasing Vi
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Technical or Customer Support Prefa
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ADSP-21367 ADSP-21368 ADSP21369 ADS
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Preface VisualDSP++ 4.5 C/C++ Compi
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VisualDSP++ Documentation Set Prefa
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1 INTRODUCTION The majority of this
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Loader Command Line Introduction If
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Initialization Code Introduction In
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A brief description of each phase f
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Introduction Download the loadable
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Introduction You can run the loader
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PROM Boot Mode Introduction After r
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Boot Streams Introduction The loade
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2 LOADER/SPLITTER FOR BLACKFIN PROC
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Loader/Splitter for Blackfin Proces
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System Reset Configuration Register
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D7 OUTPUT .LDR FILE 4-BYTE HEADER F
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Second-Stage Loader Restrictions Lo
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SPI Memory Detection Routine Loader
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Page 75 and 76: Loader/Splitter for Blackfin Proces
Page 77 and 78: P0.H = HI(EBIU_SDRRC); R0 = 0x074A(
Page 79 and 80: � Booting � SDRAM ADSP-BF536 pr
Page 85 and 86: 1-0-Byte Block Header Block Data Lo
Page 93 and 94: � The Core B Loader/Splitter for
Page 95 and 96: INITIALIZATION CODE (KERNEL WITH DE
Page 99 and 100: FLASH MEMORY INIT CODE HEADER INIT
Page 101 and 102: where: � Command-line File Search
Page 103 and 104: Blackfin Loader Command-Line Switch
Page 111 and 112: Using Base Loader Loader/Splitter f
Page 113 and 114: Table 2-11. Base Load Page Settings
Page 115 and 116: Using Second-Stage Loader Loader/Sp
Page 121 and 122: 3 LOADER FOR ADSP-2106X/21160 SHARC
Page 123 and 124: Loader for ADSP-2106x/21160 SHARC P
Page 125: Boot Mode Selection Loader for ADSP
Page 147 and 148: File Searches Loader for ADSP-2106x
Page 151 and 152: -si-revision #|none|any Loader for
Page 153 and 154: 4 LOADER FOR ADSP-21161 SHARC PROCE
Page 155 and 156: Loader for ADSP-21161 SHARC Process
Page 169 and 170: ADSP-21161 Processor Boot Streams L
Page 171 and 172: To Modify a Boot Kernel Source File
Page 175 and 176: Processor ID Numbers Loader for ADS
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Loader for ADSP-21161 SHARC Process
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File Searches Loader for ADSP-21161
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5 LOADER FOR ADSP-2126X/2136X/2137X
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Loader for ADSP-2126x/2136x/2137x S
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File Searches Loader for ADSP-2126x
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6 LOADER FOR TIGERSHARC PROCESSORS
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� EE-174: Loader for TigerSHARC P
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Boot Kernel Modification Loader for
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Loader for TigerSHARC Processors el
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TigerSHARC Command-Line Switches Lo
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Loader for TigerSHARC Processors Ta
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7 SPLITTER FOR SHARC AND TIGERSHARC
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� Most Splitter for SHARC and Tig
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Splitter for SHARC and TigerSHARC P
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A FILE FORMATS VisualDSP++ developm
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Assembly Source Files File Formats
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Build Files File Formats Build file
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Memory Map Files File Formats The l
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Table A-4. End-of-File Record Examp
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This example shows how to include t
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Table A-7. S1 Termination Record Ex
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File Formats A block of data record
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Table A-9. SPORT Data File Example
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B UTILITIES The VisualDSP++ develop
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elf2flt - ELF to BFLT File Converte
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Table B-3. BFLT File Dumper Command
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I INDEX Numerics -64 splitter switc
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BMS pins ADSP-2106x/160 processors,
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data initialization files (.dat), A
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external memory (SHARC processors)
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initialization blocks (Blackfin pro
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loader file formats (ADSP-BF535 pro
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P -p # loader switch for Blackfin,
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shared memory Blackfin processors,
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V .VAR directive, A-3 vector addres
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VisualDSP++ 4.5 Loader and Utilities Manual - Analog Devices

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