VisualDSP++ 4.5 Loader and Utilities Manual - Analog Devices

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Blackfin Processor Booting For the ADSP-BF534/BF5356/BF537processors, a pull down or pull up may be used. The on-chip boot ROM senses the polarity of this signal and asserts it by driving it to the opposite state of the external pull up/down. This PFx number is going to be user-defined and is embedded within the loader file. The loader utility embeds the number in bits [8:5] of the FLAG field within every 10-byte header. The loader utility does this by using the “-pFlag #” command-line switch where number is the intended PF flag used by the Blackfin slave and has a value between 1 and 15. � If Host (Master SPI Device) SPICLK S_SEL MOSI MISO FLAG / Interrupt ADSP-BF533 (Slave SPI) Device) SPICLK SPISS MOSI MISO Figure 2-18. Pin-to-Pin Connections for ADSP-BF531/BF532/BF533/BF534/ BF536/BF537/BF538/BF539 Processor SPI Slave Mode the “-pFlag #” switch is not used, the default value placed within bits [8:5] of the FLAG is 0, indicating that PF0 is assumed as the feedback signal to the host. Since PF0 is multiplexed with the /SPISS pin, which is mandatory for successful SPI slave boot, always use the “-pFlag #” switch and specify a value other than 0. 2-22 VisualDSP++ 4.5 Loader and Utilities Manual PFx
Loader/Splitter for Blackfin Processors ADSP-BF531/BF532/BF533/BF534/BF536/BF537/BF538/ BF539Processor in SPI Master Boot Mode For SPI master mode booting, the ADSP-BF531/BF532/BF533/BF534/ BF536/BF537/BF538/BF539 processor is configured as a SPI master connected to a SPI memory. The following shows the pin-to-pin connections needed for this mode. Figure 2-19 shows the pin-to-pin connections needed for SPI master mode. � A pull-up resistor on MISO is required for this boot mode to work properly. For this reason, the ADSP-BF531/BF532/BF533/BF534/ BF536/BF537/BF538/ BF539 processor reads a 0xFF on the MISO pin if the SPI memory is not responding (that is, no data written on the MISO pin by the SPI memory). ADSP-BF533 (Master SPI Device) SPICLK PF2 V DDEXT 10KΩ SPICLK MOSI MOSI MISO MISO Figure 2-19. Pin-to-pin connections for ADSP-BF531/BF532/BF533 Processor SPI Master Mode VisualDSP++ 4.5 Loader and Utilities Manual 2-23 CS SPI Memory (Slave SPI Device)
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Analog Devices, Inc. One Technology
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CONTENTS PREFACE Purpose of This Ma
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CONTENTS Loader Files Without a Sec
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CONTENTS ADSP-BF535 and ADSP-BF531/
Page 9 and 10: Contents File Extensions ..........
Page 11 and 12: Contents Boot Type Selection ......
Page 13 and 14: PREFACE Thank you for purchasing Vi
Page 15 and 16: Technical or Customer Support Prefa
Page 17 and 18: ADSP-21367 ADSP-21368 ADSP21369 ADS
Page 19 and 20: Preface VisualDSP++ 4.5 C/C++ Compi
Page 21 and 22: VisualDSP++ Documentation Set Prefa
Page 23 and 24: 1 INTRODUCTION The majority of this
Page 25 and 26: Loader Command Line Introduction If
Page 27 and 28: Initialization Code Introduction In
Page 29 and 30: A brief description of each phase f
Page 31 and 32: Introduction Download the loadable
Page 33 and 34: Introduction You can run the loader
Page 35 and 36: PROM Boot Mode Introduction After r
Page 37 and 38: Boot Streams Introduction The loade
Page 39 and 40: 2 LOADER/SPLITTER FOR BLACKFIN PROC
Page 41 and 42: Loader/Splitter for Blackfin Proces
Page 43 and 44: System Reset Configuration Register
Page 49 and 50: D7 OUTPUT .LDR FILE 4-BYTE HEADER F
Page 53 and 54: Second-Stage Loader Restrictions Lo
Page 59: Loader/Splitter for Blackfin Proces
Page 63 and 64: SPI Memory Detection Routine Loader
Page 77 and 78: P0.H = HI(EBIU_SDRRC); R0 = 0x074A(
Page 79 and 80: � Booting � SDRAM ADSP-BF536 pr
Page 85 and 86: 1-0-Byte Block Header Block Data Lo
Page 93 and 94: � The Core B Loader/Splitter for
Page 95 and 96: INITIALIZATION CODE (KERNEL WITH DE
Page 99 and 100: FLASH MEMORY INIT CODE HEADER INIT
Page 101 and 102: where: � Command-line File Search
Page 103 and 104: Blackfin Loader Command-Line Switch
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Using Base Loader Loader/Splitter f
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Table 2-11. Base Load Page Settings
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Using Second-Stage Loader Loader/Sp
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Loader/Splitter for Blackfin Proces
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Loader/Splitter for Blackfin Proces
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3 LOADER FOR ADSP-2106X/21160 SHARC
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Loader for ADSP-2106x/21160 SHARC P
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Boot Mode Selection Loader for ADSP
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File Searches Loader for ADSP-2106x
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-si-revision #|none|any Loader for
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4 LOADER FOR ADSP-21161 SHARC PROCE
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Loader for ADSP-21161 SHARC Process
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ADSP-21161 Processor Boot Streams L
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To Modify a Boot Kernel Source File
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Processor ID Numbers Loader for ADS
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File Searches Loader for ADSP-21161
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5 LOADER FOR ADSP-2126X/2136X/2137X
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Loader for ADSP-2126x/2136x/2137x S
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File Searches Loader for ADSP-2126x
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6 LOADER FOR TIGERSHARC PROCESSORS
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� EE-174: Loader for TigerSHARC P
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Boot Kernel Modification Loader for
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Loader for TigerSHARC Processors el
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TigerSHARC Command-Line Switches Lo
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Loader for TigerSHARC Processors Ta
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7 SPLITTER FOR SHARC AND TIGERSHARC
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� Most Splitter for SHARC and Tig
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Splitter for SHARC and TigerSHARC P
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A FILE FORMATS VisualDSP++ developm
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Assembly Source Files File Formats
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Build Files File Formats Build file
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Memory Map Files File Formats The l
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Table A-4. End-of-File Record Examp
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This example shows how to include t
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Table A-7. S1 Termination Record Ex
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File Formats A block of data record
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Table A-9. SPORT Data File Example
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B UTILITIES The VisualDSP++ develop
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elf2flt - ELF to BFLT File Converte
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Table B-3. BFLT File Dumper Command
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I INDEX Numerics -64 splitter switc
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BMS pins ADSP-2106x/160 processors,
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data initialization files (.dat), A
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external memory (SHARC processors)
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initialization blocks (Blackfin pro
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loader file formats (ADSP-BF535 pro
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P -p # loader switch for Blackfin,
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shared memory Blackfin processors,
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V .VAR directive, A-3 vector addres
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VisualDSP++ 4.5 Loader and Utilities Manual - Analog Devices

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