VisualDSP++ 4.5 Loader and Utilities Manual - Analog Devices

Blackfin Processor Booting
ADSP-BF561 and ADSP-BF566 Processor Booting
The booting sequence for the ADSP-BF561 and ADSP-BF566 dual-core
processors is similar to the ADSP-BF531/BF532/BF533 processor boot
sequence described on page 2-16. Differences occur because the
ADSP-BF561/BF566 processor has two cores: core A and core B. After
reset, core B remains idle, but core A executes the on-chip boot ROM
located at address 0xEF00 0000.
� Refer
to Chapter 3 of the ADSP-BF561 Blackfin Processor Hardware
Reference manual for information about the processor’s
operating modes and states. Refer to the “System Reset and
Power-up Configuration” section for background information on
reset and booting.
The boot ROM loads an application program from an external memory
device and starts executing that program by jumping to the start of
core A’s L1 instruction SRAM, at address 0xFFA0 0000.
Table 2-6 summarizes the boot modes and execution start addresses for
ADSP-BF561/BF566 processors.
Table 2-6. ADSP-BF561/566 Processor Boot Mode Selections
Boot Source BMODE [1:0] Execution Start Address
Reserved 000 Not applicable
Boot from 8-bit/16-bit PROM/flash memory 001 0xFFA0 0000
Boot from 8-bit addressable SPI0 serial
EEPROM
Boot from 16-bit addressable SPI0 serial
EEPROM
010 0xFFA0 0000
011 0xFFA0 0000
Reserved 111–100 Not applicable
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