VisualDSP++ 4.5 Loader and Utilities Manual - Analog Devices

Loader for ADSP-2106x/21160 SHARC Processors
A master SHARC processor may boot a slave SHARC processor by writing
to its DMACx control register and setting the packing mode (PMODE) to 00.
This allows instructions to be downloaded directly without packing. The
wait state setting of 6 on the slave processor does not affect the speed of
the download since wait states affect bus master operation only.
Link Port Boot Mode
� Link port boot is supported on all SHARC processors except
ADSP-21061 and ADSP-21065L processors.
When link-boot ADSP-2106x/21160 SHARC processors, the processor
receives data from 4-bit link buffer 4 and packs boot data into 48-bit
instructions using the appropriate DMA channels (DMA channel 6 for
ADSP-2106x processors, DMA channel 8 for ADSP-21160 processors).
Link port mode is selected when the EBOOT is low and LBOOT and BMS are
high. The external device must provide a clock signal to the link port
assigned to link buffer 4. The clock can be any frequency, up to a maximum
of the processor clock frequency. The clock falling edges strobe the
data into the link port. The most significant 4-bit nibble of the 48-bit
instruction must be downloaded first. The link port acknowledge signal
generated by the processor can be ignored during booting since the link
port cannot be preempted by another DMA channel.
Link booting is similar to host booting—the parameter registers
(IIx and Cx) for DMA channels are initialized to the same values. The
DMA channel 6 control register (DMAC6) is initialized to 0x00A0, and the
DMA channel 10 control register (DMAC10) is initialized to 0x100000. This
disables external port DMA and selects DTYPE for instruction words. The
LCTL and LCOM link port control registers are overridden during link booting
to allow link buffer 4 to receive 48-bit data.
After booting completes, the IMASK remains set, allowing DMA channel
interrupts. This interrupt must be cleared before link buffer 4 is again
enabled; otherwise, unintended link interrupts may occur.
VisualDSP++ 4.5 Loader and Utilities Manual 3-15