VisualDSP++ 4.5 Loader and Utilities Manual - Analog Devices

TigerSHARC Processor Booting
TigerSHARC Processor Booting
At chip reset, a TigerSHARC processor loads (bootstraps) a 256-instruction
program (called a boot kernel) into the processor’s internal memory.
The boot kernel program may be stored on an external PROM, a host processor,
or another TigerSHARC processor. The boot type is selected via
the processor’s boot mode select (BMS) pin as described in “Boot Type
Selection” on page 6-3. After the boot kernel loads, it executes itself and
then loads the rest of the application program and data into the processor.
The combination of the boot kernel and the application program comprises
a boot-loadable file.
TigerSHARC processors support three booting modes: EPROM/flash,
host, and link. The boot-loadable files for each of these modes pack the
boot data into 32-bit instructions and use a DMA channel of the processor’s
DMA controller to boot-load the instructions.
Additionally, there are several no-boot modes, which do not require
kernels.
In EPROM/flash boot mode, the loader utility generates a PROM
image that contains all project data and loader code. The project
data is then stored in an 8-bit wide external EPROM. After reset,
the processor performs a special booting scenario, reading the
EPROM content through the processor’s external port and initializing
on-chip and off-chip memories.
In host boot mode, the processor accepts boot data from a 32- or
64-bit synchronous microprocessor (host). The host writes a
boot-loadable file to the processor’s AUTODMA register through the
processor’s external port, one 32-bit word at a time. Once the last
word is written, the processor takes over and runs the user code.
6-2 VisualDSP++ 4.5 Loader and Utilities Manual