VisualDSP++ 4.5 Loader and Utilities Manual - Analog Devices

Loader/Splitter for Blackfin Processors
ADSP-BF531/BF532/BF533/BF534/BF536/BF537/BF538/
BF539 Processor On-Chip Boot ROM
The on-chip boot ROM for ADSP-BF531/BF532/BF533/BF534/
BF536/BF537/BF538/BF539 processors does the following.
1. Sets up supervisor mode by exiting the RESET interrupt service
routine and jumping into the lowest priority interrupt (IVG15).
Note that the on-chip boot ROM of the ADSP-BF534/BF536 and
ADSP-BF537 processors executes at the Reset priority level, does
not degrade to the lowest priority interrupt.
2. Checks whether the RESET was a software reset and, if so, whether
to skip the entire sequence and jump to the start of L1 memory
(0xFFA0 0000 for ADSP-BF533/BF534/BF536/BF537/BF539
processors; 0xFFA0 8000 for ADSP-BF531/BF532/BF538) for
execution. The on-chip boot ROM does this by checking the
NOBOOT bit (bit 4) of the system reset configuration register (SYSCR).
See Figure 2-16. If bit 4 is not set, the on-chip boot ROM performs
the full boot sequence. If bit 4 is set, the on-chip boot ROM
bypasses the full boot sequence and jumps to the start of L1
memory.
X - state is initialized from mode pins during hardware reset
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0xFFC0 0104
0 0 0 0 0 0 0 0 0 0 0 0 0 X X X Reset = dependent on pin
values
NOBOOT (No Boot on Software Reset)
0 - Use BMODE to determine
boot source
1 - Start executing from the
the EVT1 vector.
EVT1 defaults to 0xFFA00000,
except the ADSP-BF531/BF532
and ADSP-BF538 processors,
where it defaults to 0xFFA08000.
Figure 2-16. System Reset Configuration Register
BMODE[2:0] (Boot Mode) - RO
The BMODE bit field represents
the BMODE pin settings. Various
processors populate two, three or
four bits according to the number
of featured BMODE pins (see
Table 2-2 and Table 2-3.
VisualDSP++ 4.5 Loader and Utilities Manual 2-19