characterization, modeling, and design of esd protection circuits

84 Chapter 3. Simulation: Methods and Applications
robust device. This directly contradicts the statement made by Mayaram et al. [13] and a
similar assumption made by Diaz et al. [24] that 2D ESD simulation overestimates the
peak temperature in a device and therefore underestimates its robustness. Eq. (3.38) also
may explain why Diaz found that 2D simulations overestimated the power to failure in
MOSFETs for times greater than 20µs, although at such long times the high-temperature
region has extended well beyond the drain junction depletion region, which means the
assumptions of the thermal model no longer precisely hold.
In the next chapter, we will see that in simulations of MOSFET protection devices the
capability of 2D simulations to model power to failure for ESD stresses is not nearly as
poor as suggested by Fig. 3.33. The ability to overcome the discrepancy between the 2D
and 3D thermal models stems from the limitations of the assumptions made in the models
when applied to real MOS structures. It was mentioned in Section 2.2.2 that the thermal
box model is not completely accurate because the gate oxide at the top of the box acts like
an insulator, not a conductor, so heat flow in this direction is greatly restricted and the
peak temperature must be higher than predicted by the model. In an actual MOSFET, the
reduction in failure power due to the insulating surface of the gate oxide is estimated to be
significantly less than a factor of two [32]. By running a few 2D simulations with an
insulating thermal boundary condition on one side of the b × c rectangle, it was
determined that due to the insulating surface the peak temperature increases by a factor of
two when the sides of the rectangle are equal. For unequal sides, this factor of two is
roughly multiplied by the ratio of b⁄ c,
where b is the dimension of the side which is
insulated. Since the side of the box along the gate is usually longer than the side equal to
the drain junction depth, the increase in peak temperature due to the insulating gate may
be proportionately greater in 2D MOSFET simulations than in actual structures, thereby
reducing the 2D failure power to a level closer to the 3D case.
The other major assumption of the thermal box model which is violated in MOSFET
simulations as well as in real devices is that for longer ESD pulse times (greater than a few
hundred nanoseconds), the semiconductor region outside the box is no longer fixed at
300K and therefore cannot act as a perfect heat sink. As in the case for the gate oxide, the
lack of an ideal heat sink implies that the peak temperature in the box will be greater than
predicted by the model, which in turn implies that the power to failure will be lower than
predicted. It is not obvious whether the actual boundary conditions surrounding the highfield
region increase or decrease the disparity between real structures and 2D simulations.