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characterization, modeling, and design of esd protection circuits

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202 Bibliography<br />

[30] “ATLAS 2D Device Simulation Framework User’s Manual, Edition 2,” Silvaco<br />

International, Santa Clara, CA, 1994.<br />

[31] H.S. Carslaw <strong>and</strong> J.C. Jaeger, Conduction <strong>of</strong> Heat in Solids, 2nd Ed., Oxford,<br />

Clarendon Press, 1959.<br />

[32] A. Amerasekera, A. Chatterjee, <strong>and</strong> M.-C. Chang, “Prediction <strong>of</strong> ESD Robustness in<br />

a Process Using 2-D Device Simulations,” Proc. IEEE Int. Reliability Physics<br />

Symp., 1993, pp. 161-167.<br />

[33] A. Chatterjee, T. Polgreen, <strong>and</strong> A. Amerasekera, “Design <strong>and</strong> Simulation <strong>of</strong> a 4 kV<br />

ESD Protection Circuit for a 0.8µm BiCMOS Process,” IEDM Tech. Dig., 1991,<br />

pp. 913-916.<br />

[34] O. J. McAteer, Electrostatic Discharge Control, McGraw-Hill, New York, 1990.<br />

[35] H. Hyatt, H. Calvin, an H. Mellberg, “A Closer Look at the Human ESD Event,”<br />

Proc. 3rd EOS/ESD Symp., 1981, pp. 1-8.<br />

[36] O.J. McAteer, “Electrostatic Damage in Hybrid Assemblies,” Annual Reliability <strong>and</strong><br />

Maintainability Symposium Proceedings, 1978, pp. 434-442.<br />

[37] Z. Yu, D. Chen, R.J.G. Goossens, <strong>and</strong> R.W. Dutton, “Accurate Modeling <strong>and</strong><br />

Numerical Techniques in Simulation <strong>of</strong> Impact-Ionization Effects on BJT<br />

Characteristics,” IEDM Tech. Dig., 1991, pp. 901-904.<br />

[38] D.C. Wunsch <strong>and</strong> R.R. Bell, “Determination <strong>of</strong> Threshold Failure Levels <strong>of</strong><br />

Semiconductor Diodes <strong>and</strong> Transistors due to Pulse Voltages,” IEEE Trans. Nucl.<br />

Sci., vol. NS-15, Dec. 1968, pp. 244-259.<br />

[39] V.M. Dwyer, A.J. Franklin, <strong>and</strong> D.S. Campbell, “Thermal Failure in Semiconductor<br />

Devices,” Solid-State Electronics, vol. 33, 1990, pp. 553-560.<br />

[40] D.L. Lin, “ESD Sensitivity <strong>and</strong> VLSI Technology Trends: Thermal Breakdown <strong>and</strong><br />

Dielectric Breakdown,” Proc. 15th EOS/ESD Symp., 1993, pp. 73-81.<br />

[41] C. Duvvury <strong>and</strong> C. Diaz, “Dynamic Gate Coupling <strong>of</strong> NMOS for Efficient Output<br />

ESD Protection,” Proc. IEEE Int. Reliability Physics Symp., 1992, pp. 141-150.

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