characterization, modeling, and design of esd protection circuits

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28 Chapter 2. ESD Circuit Characterization and Design Issues V Fig. 2.9 The screen capture shows the current and voltage response to a 15V, 150ns input pulse. The device voltage breaks down and snaps back in the first few nanoseconds of the pulse. Fig. 2.10 Second breakdown is observed as a drop in the device voltage and rise in device current about 72ns into the 36V, 150ns input pulse. V I I V
2.2. Transmission Line Pulsing 29 ESD event unless the rise time of the pulse is much longer than that of the TLP pulse. Experimentally the difference in Vt1 between dc sweeps and TLP pulses with 3ns rise times is only one or two volts, so TLP-measured Vt1 values are still indicative of the maximum input voltage created by pulses with much longer rise times. 2.2.2 Failure Power vs. Time to Failure The short-duration pulses used to generate an I-V curve with TLP should be representative of actual ESD events. For example, a 100ns square-wave pulse provides a stress similar to a human-body model pulse, which has a decay time of approximately 150ns. A similar I-V curve can be generated with a well-controlled quasi-steady state current sweep, but the second-breakdown point will occur at a lower current due to the longer time spent at each stress level (there is also a dependence of Vt1 , It1 , and other parameters on the height and rise time of the input pulse). This is more representative of EOS damage. Intuitively, one expects a device to fail at a lower pulse height if the pulse duration is longer. To quantify this idea, a 3D thermal model has been proposed which defines four distinct regions of power-to-failure vs. time-to failure [23,38,39]. This model assumes a rectangular-box region of device heating in the drain-side junction depletion region of a MOSFET with a spatially uniform, time-invariant power source ( Watts/cm 3 H = J ⋅ E ); constanttemperature boundary conditions on all sides of the box (an infinite heat sink); and no heating outside the box. As shown in Fig. 2.11, the length of the box, a, is equal to the poly gate gate oxide c b a p sub Fig. 2.11 3D thermal box region (dotted lines) of heat dissipation in an NMOS transistor subjected to a positive ESD pulse. The dimension a is equal to the device width, b is related to the gate length, and c is approximately equal to the diffusion depth. n + n LDD
Page 1 and 2: CHARACTERIZATION, MODELING, AND DES
Page 3 and 4: Abstract For more than 20 years, su
Page 5 and 6: Acknowledgments This work could not
Page 7 and 8: Contents Abstract iii Acknowledgmen
Page 9 and 10: 6 Conclusion 165 6.1 Contributions
Page 11 and 12: List of Figures 1.1 ESD protection
Page 13 and 14: 3.32 Simulated 1/∆T vs. time and
Page 15 and 16: A.65 The output file, bvceo.out, fo
Page 17 and 18: Chapter 1 Introduction Electrostati
Page 19 and 20: 1.1. ESD in the Integrated Circuit
Page 21 and 22: 1.2. Characterizing ESD in Integrat
Page 23 and 24: 1.3. Protecting Integrated Circuits
Page 25 and 26: 1.4. Numerical Simulation 9 simulat
Page 27 and 28: 1.5. Design Methodology 11 process.
Page 29 and 30: 1.6. Outline and Contributions 13 A
Page 31 and 32: Chapter 2 ESD Circuit Characterizat
Page 33 and 34: 2.1. Classical ESD Characterization
Page 35 and 36: 2.2. Transmission Line Pulsing 19 i
Page 37 and 38: 2.2. Transmission Line Pulsing 21 (
Page 39 and 40: 2.2. Transmission Line Pulsing 23 (
Page 41 and 42: 2.2. Transmission Line Pulsing 25 I
Page 43: 2.2. Transmission Line Pulsing 27 I
Page 47 and 48: 2.2. Transmission Line Pulsing 31 w
Page 49 and 50: 2.2. Transmission Line Pulsing 33 a
Page 51 and 52: 2.2. Transmission Line Pulsing 35 F
Page 53 and 54: 2.3. Overview of Protection Circuit
Page 61 and 62: 2.4. Dependence of Critical MOSFET
Page 63 and 64: 2.4. Dependence of Critical MOSFET
Page 65 and 66: 2.5. Design Methodology 49 the subs
Page 67 and 68: 2.5. Design Methodology 51 The perf
Page 69 and 70: 2.5. Design Methodology 53 enter se
Page 71 and 72: Chapter 3 Simulation: Methods and A
Page 73 and 74: 3.1. Lattice Temperature and Temper
Page 81 and 82: 3.2. Curve Tracing 65 line (c) in F
Page 83 and 84: 3.3. Mixed Mode Simulation 67 x n-1
Page 85 and 86: 3.3. Mixed Mode Simulation 69 V c C
Page 87 and 88: 3.4. Previous ESD Applications 71 v
Page 89 and 90: 3.4. Previous ESD Applications 73 I
Page 91 and 92: 3.5. Extraction of MOSFET I-V Param
Page 93 and 94: 3.6. Extraction of MOSFET Pf vs. tf
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3.6. Extraction of MOSFET Pf vs. tf
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3.7. Simulation of Dielectric Failu
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Chapter 4 Simulation: Calibration a
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4.1. Calibration Procedure 97 and t
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4.1. Calibration Procedure 99 conta
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4.1. Calibration Procedure 101 4.40
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4.1. Calibration Procedure 103 Afte
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4.1. Calibration Procedure 105 past
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4.1. Calibration Procedure 107 whic
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4.1. Calibration Procedure 109 simu
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4.1. Calibration Procedure 111 (a)
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4.1. Calibration Procedure 113 wher
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4.1. Calibration Procedure 115 peri
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4.1. Calibration Procedure 117 simu
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4.1. Calibration Procedure 119 volt
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4.2. MOSFET Snapback I-V Results 12
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4.2. MOSFET Snapback I-V Results 12
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4.3. Device Failure Results 125 V t
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4.3. Device Failure Results 127 alr
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4.3. Device Failure Results 129 act
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4.3. Device Failure Results 131 (a)
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4.3. Device Failure Results 133 (a)
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4.4. Design Example 135 reached, th
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4.4. Design Example 137 Using value
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Chapter 5 Design and Optimization o
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5.1. Methodology 141 5.1 Methodolog
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5.1. Methodology 143 W L DGS SGS Co
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5.1. Methodology 145 reaches its pe
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5.1. Methodology 147 the same withs
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5.1. Methodology 149 various respon
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5.1. Methodology 151 needed to desc
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5.1. Methodology 153 The actual pat
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5.2. Application 155 To determine h
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5.3. Analysis 157 are flat, a direc
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5.3. Analysis 159 assumed to be iso
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5.4. Optimization 161 Qualitatively
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5.5. Summary of Design Methodology
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Chapter 6 Conclusion In the integra
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6.1. Contributions 167 TLP was show
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6.2. Future Work 169 most ESD quali
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6.2. Future Work 171 Significant wo
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Appendix A Tracer User’s Manual S
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A.3. CONTROL Card 175 A.3 CONTROL C
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A.4. FIXED Card 177 A.4 FIXED Card
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A.5. OPTION Card 179 • DAMP is a
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A.5. OPTION Card 181 A.5.4 Examples
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A.6. SOLVE Card 183 if the voltage
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A.7. Input Deck Specifications 185
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A.9. Examples 187 column contains c
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A.9. Examples 189 fixed num = 1 typ
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A.9. Examples 191 Collector Current
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A.9. Examples 193 title mes.pis mes
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A.9. Examples 195 simulator to use.
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A.9. Examples 197 #Soln #Vctrl Ictr
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Bibliography [1] T.J. Green and W.K
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Bibliography 201 [20] C. Duvvury, R
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Bibliography 203 [42] S.M. Sze, Phy
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Bibliography 205 [63] R. van Overst
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