characterization, modeling, and design of esd protection circuits

4.1. Calibration Procedure 101
4.40e. Wafer-level I-V data can be taken at temperatures up to around 500K using a hot
chuck and then used as a basis for calibrating model coefficients in high-temperature
simulations. For calibration of this AMD technology, however, it is assumed that the
temperature dependences in the mobility and II models, which are qualitatively correct
and have been fit to high-temperature data of other technologies [47,49], are accurate
enough using default coefficient values. The benefit of high-temperature calibration is
actually limited because for sub-microsecond ESD events the high-temperature region is
localized--perhaps covering as little as 10 percent of the simulation space--and thus the
temperature dependence of the mobility and II models may not have much effect on the
overall I-V curve. Also, these models have only been shown to be valid up to a certain
temperature, e.g., 460K for mobility [47], close to the limit of hot-chuck measurements,
but critical ESD effects occur at higher temperatures. And even if the mobility and II
models are calibrated at high temperatures, other simulation models are suspect. For
example, at 900K the band-gap shrinkage model predicts a band gap energy about 40mV
higher than the measured value [60]. Instead of calibrating mobility and II coefficients at
high temperatures to fit ESD thermal-failure simulations, the approach taken here is to
adjust the thermal boundary conditions, i.e., the placement of the thermal contacts and use
of lumped thermal resistors and capacitors, to match simulated and experimental data.
Since the true thermal boundary conditions are not known exactly, adjusting the thermal
contacts and lumped elements to fit simulated thermal failure to ESD data is a reasonable
way to determine their values. Discussion of the calibration of thermal effects is not taken
up until Section 4.1.4. For all of the MOSFET simulations described in this subsection,
the initial lattice temperature is set to 297K and is allowed to increase in regions of heat
generation (Eq. (3.15)) as determined by the thermal diffusion equation (Eq. (2.2)).
Constant-temperature boundary conditions are placed on the bottom and sides of the
simulation structures as a simple way of modeling the large heat sink of the bulk silicon,
but these are not really important because the maximum temperature during any of the
MOSFET simulations is less than 310K.
Calibration of the Lombardi mobility model began with simulations of the gate characteristic
shown in Fig. 4.40b. To reduce simulation time, a one-carrier (electron) solution
method was used because hole current is negligible in an NMOS transistor in its normal
operating range. This implies that only the electron mobility coefficients are adjusted during
calibration. Initial simulations of the 0.5µm and 3.0µm structures using default values