characterization, modeling, and design of esd protection circuits

Chapter 4
Simulation: Calibration and
Results
To apply the concepts of ESD circuit characterization, simulation, and design discussed in
Chapters 2 and 3, special MOSFET test structures were laid out in an Advanced Micro
Devices 0.5µm, 3.3V CMOS technology and then tested with the transmission-line
pulsing setup described in Section 2.2.4. These parametric structures are not designed to
protect actual input/output (I/O) circuits but rather to determine the dependence of the
ESD circuit parameters on device width, gate length, and contact-to-gate spacing. All
structures are single fingered (as opposed to actual protection circuits, which are usually
multiple fingered) and make use of a resist mask to block silicidation between the source/
drain contacts and the gate. There is one exception: due to space limitations, the structures
with varying gate length were not laid out on the special test tiles but rather were taken
from a standard, fully salicided (self-aligned silicide) test tile. Software was written and
used to garner the TLP data, extract I-V parameters from the data, and perform statistical
analysis on the I-V parameters.
Numerical two-dimensional (2D) device simulation of the ESD structures was performed
using TMA-MEDICI [29], which was chosen over Stanford’s PISCES-2ET [44] because
the lattice-temperature code in PISCES was not fully debugged at the time simulations
began. The simulation models presented in Chapter 3 were initially calibrated against
standard MOSFET characterization curves of two salicided test structures with different
gate lengths and then were calibrated against TLP data from the special test structures to
model the snapback and thermal effects. Calibration refers to the adjustment of simulation
model coefficients which yields simulated device I-V and failure characteristics that
match the experimentally determined characteristics of real devices. In the next section,
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