characterization, modeling, and design of esd protection circuits

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6 Chapter 1. Introduction work needs to be done to understand the mechanisms of the CDM and to develop a standardized test, the CDM is now receiving much more attention in the IC industry as a result of the past focus on prevention and protection of HBM-related ESD. A relatively new testing technique, transmission-line pulsing (TLP), takes a different approach to characterizing ESD than the classical models described above [8,21-24]. Instead of duplicating a “real-life” event such as electrostatic discharge from a finger or machine, TLP stresses IC pins with square-wave pulses of varying magnitude and length in order to study how a protection circuit responds to stimuli throughout the EOS/ESD spectrum. Short pulse lengths (on the order of 100ns to 1µs) allow extraction of information without causing unintentional thermal damage to the device. The simple square-wave inputs of the TLP method allow easy extraction of the transient current-voltage (I-V) curve of a protection circuit. Additionally, they reveal the pulse power needed to drive a circuit into second breakdown for a given pulse length. Using a spectrum of pulse lengths, a power-to-failure vs. time-to-failure (Pf vs. tf ) curve can be extracted. The I-V and Pf vs. tf curves are very useful in determining the overall robustness of a protection circuit and in locating the weak point of the circuit. It has been suggested that transmission-line pulsing be used as a qualifier of ESD reliability, but this will probably not happen until correlations are drawn between TLP-generated failures and the classical ESD model-generated failures (TLP-HBM correlation is demonstrated for a range of transistor designs in Chapter 5). The transmission-line pulsing method and its merits will be fully discussed in Chapter 2. Application of TLP to the study of ESD is an important topic of this thesis. 1.3 Protecting Integrated Circuits from ESD The importance of ESD protection circuits and the increasing difficulty of designing effective circuits for new technologies were discussed at the beginning of this chapter. A protection circuit serves two main purposes: providing a current path during a high-stress event and clamping the voltage at the stressed pin below the gate-oxide breakdown level. Additionally, the protection circuit itself should not become severely damaged during an ESD event. Although the odds of having the same pair of pins stressed more than once is small, it is important that the protection circuit not become leaky and degrade chip performance. Also, in the case of output-protection circuits which double as output drivers, long-term reliability may be reduced if damage is incurred. For example, it has been shown that MOSFETs driven deep into snapback during an ESD stress may suffer
1.3. Protecting Integrated Circuits from ESD 7 hole trapping in the gate oxide as well as interface-state generation, leading to a shift in the threshold voltage [25]. The hole trapping can increase the susceptibility to timedependent dielectric breakdown (TDDB) of the gate oxide. (TDDB refers to the observed phenomenon that the higher a stress voltage is, the less time it takes to damage the oxide being stressed.) To avoid being damaged, protection circuits should minimize self-heating by keeping current densities and electric fields in the silicon low and prevent dielectric breakdown of the gate oxides in the protection circuit by minimizing the electric fields across the oxides. Although this thesis focuses on protection circuits between input/output (I/O) pins and supply pins, ESD phenomena can occur across any pair of pins, e.g., I/O vs. I/O and VCC vs. VSS . Protection circuits are not placed between the I/O pins of a package, and even though a protection diode or transistor is usually placed between the two supply pins, there is no guarantee that an electrostatic discharge will go through this path because the circuits in the chip may provide a lower-resistance path. ESD events between I/Os and between supplies lead to “far-internal” damage, i.e., the discharge paths lead through the actual working circuit, and thus damage can occur in any number of places [20]. Modeling of this behavior and design of protection are difficult because the discharge path is not known a priori and more circuit elements are involved. A few examples of ESD protection circuits are shown in Fig. 1.1. If the circuit of Fig. 1.1a is powered up, diode D1 will turn on and conduct current for any input voltage greater than VCC + Vd , where Vd is the forward diode drop. Similarly, diode D2 will clamp any negative voltage below VSS - Vd . If the chip is not powered up and an ESD pulse is incident between the input and, say, VSS , the voltage will be clamped at either the reverse breakdown voltage of the diode for a positive pulse or at -Vd for a negative pulse. The PMOS (M1) and NMOS (M2) devices of Fig. 1.1b behave similarly, with the drainsubstrate junctions taking the place of the diodes. One major difference is that the drainsubstrate junction reverse breakdown triggers the MOS device into a snapback mode in which the drain voltage drops due to the turn-on of the lateral parasitic bipolar transistor formed by the drain, channel, and source regions. Note that the output buffer is self protecting, i.e., the transistors of the output buffer serve as the protection circuit. Finally, Fig. 1.1c is an example of a more complex input protection circuit consisting of two NMOS devices and a well resistor. The merits of this circuit as well as a more complete description of the functionality of all the circuits are presented in Chapter 2.
Page 1 and 2: CHARACTERIZATION, MODELING, AND DES
Page 3 and 4: Abstract For more than 20 years, su
Page 5 and 6: Acknowledgments This work could not
Page 7 and 8: Contents Abstract iii Acknowledgmen
Page 9 and 10: 6 Conclusion 165 6.1 Contributions
Page 11 and 12: List of Figures 1.1 ESD protection
Page 13 and 14: 3.32 Simulated 1/∆T vs. time and
Page 15 and 16: A.65 The output file, bvceo.out, fo
Page 17 and 18: Chapter 1 Introduction Electrostati
Page 19 and 20: 1.1. ESD in the Integrated Circuit
Page 21: 1.2. Characterizing ESD in Integrat
Page 25 and 26: 1.4. Numerical Simulation 9 simulat
Page 27 and 28: 1.5. Design Methodology 11 process.
Page 29 and 30: 1.6. Outline and Contributions 13 A
Page 31 and 32: Chapter 2 ESD Circuit Characterizat
Page 33 and 34: 2.1. Classical ESD Characterization
Page 35 and 36: 2.2. Transmission Line Pulsing 19 i
Page 37 and 38: 2.2. Transmission Line Pulsing 21 (
Page 39 and 40: 2.2. Transmission Line Pulsing 23 (
Page 41 and 42: 2.2. Transmission Line Pulsing 25 I
Page 43 and 44: 2.2. Transmission Line Pulsing 27 I
Page 45 and 46: 2.2. Transmission Line Pulsing 29 E
Page 47 and 48: 2.2. Transmission Line Pulsing 31 w
Page 49 and 50: 2.2. Transmission Line Pulsing 33 a
Page 51 and 52: 2.2. Transmission Line Pulsing 35 F
Page 53 and 54: 2.3. Overview of Protection Circuit
Page 61 and 62: 2.4. Dependence of Critical MOSFET
Page 63 and 64: 2.4. Dependence of Critical MOSFET
Page 65 and 66: 2.5. Design Methodology 49 the subs
Page 67 and 68: 2.5. Design Methodology 51 The perf
Page 69 and 70: 2.5. Design Methodology 53 enter se
Page 71 and 72: Chapter 3 Simulation: Methods and A
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3.1. Lattice Temperature and Temper
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3.2. Curve Tracing 65 line (c) in F
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3.3. Mixed Mode Simulation 67 x n-1
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3.3. Mixed Mode Simulation 69 V c C
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3.4. Previous ESD Applications 71 v
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3.4. Previous ESD Applications 73 I
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3.5. Extraction of MOSFET I-V Param
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3.6. Extraction of MOSFET Pf vs. tf
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3.7. Simulation of Dielectric Failu
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Chapter 4 Simulation: Calibration a
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4.1. Calibration Procedure 97 and t
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4.1. Calibration Procedure 99 conta
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4.1. Calibration Procedure 101 4.40
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4.1. Calibration Procedure 103 Afte
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4.1. Calibration Procedure 105 past
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4.1. Calibration Procedure 107 whic
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4.1. Calibration Procedure 109 simu
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4.1. Calibration Procedure 111 (a)
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4.1. Calibration Procedure 113 wher
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4.1. Calibration Procedure 115 peri
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4.1. Calibration Procedure 117 simu
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4.1. Calibration Procedure 119 volt
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4.2. MOSFET Snapback I-V Results 12
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4.2. MOSFET Snapback I-V Results 12
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4.3. Device Failure Results 125 V t
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4.3. Device Failure Results 127 alr
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4.3. Device Failure Results 129 act
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4.3. Device Failure Results 131 (a)
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4.3. Device Failure Results 133 (a)
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4.4. Design Example 135 reached, th
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4.4. Design Example 137 Using value
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Chapter 5 Design and Optimization o
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5.1. Methodology 141 5.1 Methodolog
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5.1. Methodology 143 W L DGS SGS Co
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5.1. Methodology 145 reaches its pe
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5.1. Methodology 147 the same withs
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5.1. Methodology 149 various respon
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5.1. Methodology 151 needed to desc
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5.1. Methodology 153 The actual pat
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5.2. Application 155 To determine h
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5.3. Analysis 157 are flat, a direc
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5.3. Analysis 159 assumed to be iso
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5.4. Optimization 161 Qualitatively
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5.5. Summary of Design Methodology
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Chapter 6 Conclusion In the integra
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6.1. Contributions 167 TLP was show
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6.2. Future Work 169 most ESD quali
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6.2. Future Work 171 Significant wo
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Appendix A Tracer User’s Manual S
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A.3. CONTROL Card 175 A.3 CONTROL C
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A.4. FIXED Card 177 A.4 FIXED Card
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A.5. OPTION Card 179 • DAMP is a
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A.5. OPTION Card 181 A.5.4 Examples
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A.6. SOLVE Card 183 if the voltage
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A.7. Input Deck Specifications 185
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A.9. Examples 187 column contains c
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A.9. Examples 189 fixed num = 1 typ
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A.9. Examples 191 Collector Current
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A.9. Examples 193 title mes.pis mes
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A.9. Examples 195 simulator to use.
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A.9. Examples 197 #Soln #Vctrl Ictr
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Bibliography [1] T.J. Green and W.K
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Bibliography 201 [20] C. Duvvury, R
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Bibliography 203 [42] S.M. Sze, Phy
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Bibliography 205 [63] R. van Overst
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