characterization, modeling, and design of esd protection circuits

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120 Chapter 4. Simulation: Calibration and Results modeling of thermal failure impossible. In the comparison of the 2D and 3D thermal box models in Section 3.6, the 2D model was found to overestimate the failure power, not underestimate it as in this case. This suggests that the problem lies not in the abilities of 2D simulation but in insufficient calibration of the high-current, high-temperature portion of the I-V curve. More work needs to be done to determine if quantitative power-to-failure vs. time-to-failure simulations can be accomplished using the chosen simulation models. Given the results of the simulations in this subsection, it is clear that the thermal boundary conditions must be set to maximize heat dissipation if the models are to be used with the coefficients determined by the calibration procedures described in this chapter. This is the approach taken in the (qualitative) failure simulations of Section 4.3. 4.2 MOSFET Snapback I-V Results In this section and the following section, selected results will be presented for snapback I-V curves and device failure, respectively, from transmission-line pulsing tests and TMA- MEDICI 2D simulations. TLP experiments were performed on structures from the AMD 0.5µm-technology described near the beginning of this chapter, and the simulation results are based on the calibrated models detailed in Section 4.1. In the experiments and transient simulations, parametric NMOS transistors were stressed with positive pulses incident at the drain with the source, gate, and substrate grounded (except where noted) as depicted in the inset of Fig. 4.41. In dc simulations, the drain was swept with the source, gate, and substrate grounded, as in Fig. 4.42. The results are presented as a sort of potpourri with the intention of illustrating the uses of TLP discussed in Chapter 2 and the related simulation applications discussed in Chapter 3; comparisons will be made between simulation and experiment where applicable. Many of the individual results will be brought together in Section 4.4 to form the basis of an ESD circuit-design example. Examples of the I-V curves generated by a TLP experiment and a dc-sweep simulation were already given in Fig. 4.41 and Fig. 4.42, respectively. Section 4.1.3 discussed the relatively weak dependence of the trigger voltage, Vt1 , and snapback voltage, Vsb , on contact-to-gate spacing observed in the TLP tests and simulations. There is a definite dependence of the snapback resistance on CGS, though, and this is shown in Fig. 4.45 for 50/0.75µm devices. Experimental values are the average linear least-squares fit of the I-V points between snapback and second breakdown, while each simulated value is taken as the slope of the dc-sweep I-V curve just after snapback as specified by Section 4.1.3.
4.2. MOSFET Snapback I-V Results 121 R sb / Ω 16 12 8 4 Experiment Simulation 0 0 2 4 6 8 10 Source and Drain Contact-to-Gate Spacing / µm Fig. 4.45 Experimental and simulated snapback resistance, R sb , vs. contact-togate spacing for a 50/0.75µm MOSFET test structure. The contact-togate spacing refers to the distance from the drain contacts to the gate edge and the source contacts to the gate edge. There is good agreement between simulation and experiment, and both show that Rsb has a linear dependence on CGS for CGS between 3.0 and 8.0µm. This linear dependence might be expected because increasing CGS increases the series resistance from drain to source. However, note that if the line is extrapolated to zero CGS, Rsb is negative, indicating that extrapolating linearly to lower CGS values will lead to incorrect results. This could be due to experimental uncertainty and to uncertainty in the simulation extractions, although the agreement between the two curves suggests the values are correct. Heating effects also play a role in determining Rsb , as seen in Fig. 4.41, in which the line with slope 1 ⁄ Rsb, determined by the least-squares fit of the points between snapback and second breakdown, has a smaller slope (greater resistance) than the line formed by the first few I-V points after snapback, a result of the increased resistance at higher currents when device heating becomes significant. If the effect of heating lessens as
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CHARACTERIZATION, MODELING, AND DES
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Abstract For more than 20 years, su
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Acknowledgments This work could not
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Contents Abstract iii Acknowledgmen
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6 Conclusion 165 6.1 Contributions
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List of Figures 1.1 ESD protection
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3.32 Simulated 1/∆T vs. time and
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A.65 The output file, bvceo.out, fo
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Chapter 1 Introduction Electrostati
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1.1. ESD in the Integrated Circuit
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1.2. Characterizing ESD in Integrat
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1.3. Protecting Integrated Circuits
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1.4. Numerical Simulation 9 simulat
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1.5. Design Methodology 11 process.
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1.6. Outline and Contributions 13 A
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Chapter 2 ESD Circuit Characterizat
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2.1. Classical ESD Characterization
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2.2. Transmission Line Pulsing 19 i
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2.2. Transmission Line Pulsing 21 (
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2.2. Transmission Line Pulsing 23 (
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2.2. Transmission Line Pulsing 25 I
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2.2. Transmission Line Pulsing 27 I
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2.2. Transmission Line Pulsing 29 E
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2.2. Transmission Line Pulsing 31 w
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2.2. Transmission Line Pulsing 33 a
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2.2. Transmission Line Pulsing 35 F
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2.3. Overview of Protection Circuit
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2.4. Dependence of Critical MOSFET
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2.4. Dependence of Critical MOSFET
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2.5. Design Methodology 49 the subs
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2.5. Design Methodology 51 The perf
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2.5. Design Methodology 53 enter se
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Chapter 3 Simulation: Methods and A
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3.1. Lattice Temperature and Temper
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3.2. Curve Tracing 65 line (c) in F
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3.3. Mixed Mode Simulation 67 x n-1
Page 85 and 86: 3.3. Mixed Mode Simulation 69 V c C
Page 87 and 88: 3.4. Previous ESD Applications 71 v
Page 89 and 90: 3.4. Previous ESD Applications 73 I
Page 91 and 92: 3.5. Extraction of MOSFET I-V Param
Page 93 and 94: 3.6. Extraction of MOSFET Pf vs. tf
Page 103 and 104: 3.7. Simulation of Dielectric Failu
Page 111 and 112: Chapter 4 Simulation: Calibration a
Page 113 and 114: 4.1. Calibration Procedure 97 and t
Page 115 and 116: 4.1. Calibration Procedure 99 conta
Page 117 and 118: 4.1. Calibration Procedure 101 4.40
Page 119 and 120: 4.1. Calibration Procedure 103 Afte
Page 121 and 122: 4.1. Calibration Procedure 105 past
Page 123 and 124: 4.1. Calibration Procedure 107 whic
Page 125 and 126: 4.1. Calibration Procedure 109 simu
Page 127 and 128: 4.1. Calibration Procedure 111 (a)
Page 129 and 130: 4.1. Calibration Procedure 113 wher
Page 131 and 132: 4.1. Calibration Procedure 115 peri
Page 133 and 134: 4.1. Calibration Procedure 117 simu
Page 135: 4.1. Calibration Procedure 119 volt
Page 139 and 140: 4.2. MOSFET Snapback I-V Results 12
Page 141 and 142: 4.3. Device Failure Results 125 V t
Page 143 and 144: 4.3. Device Failure Results 127 alr
Page 145 and 146: 4.3. Device Failure Results 129 act
Page 147 and 148: 4.3. Device Failure Results 131 (a)
Page 149 and 150: 4.3. Device Failure Results 133 (a)
Page 151 and 152: 4.4. Design Example 135 reached, th
Page 153 and 154: 4.4. Design Example 137 Using value
Page 155 and 156: Chapter 5 Design and Optimization o
Page 157 and 158: 5.1. Methodology 141 5.1 Methodolog
Page 159 and 160: 5.1. Methodology 143 W L DGS SGS Co
Page 161 and 162: 5.1. Methodology 145 reaches its pe
Page 163 and 164: 5.1. Methodology 147 the same withs
Page 165 and 166: 5.1. Methodology 149 various respon
Page 167 and 168: 5.1. Methodology 151 needed to desc
Page 169 and 170: 5.1. Methodology 153 The actual pat
Page 171 and 172: 5.2. Application 155 To determine h
Page 173 and 174: 5.3. Analysis 157 are flat, a direc
Page 175 and 176: 5.3. Analysis 159 assumed to be iso
Page 177 and 178: 5.4. Optimization 161 Qualitatively
Page 179 and 180: 5.5. Summary of Design Methodology
Page 181 and 182: Chapter 6 Conclusion In the integra
Page 183 and 184: 6.1. Contributions 167 TLP was show
Page 185 and 186: 6.2. Future Work 169 most ESD quali
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6.2. Future Work 171 Significant wo
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Appendix A Tracer User’s Manual S
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A.3. CONTROL Card 175 A.3 CONTROL C
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A.4. FIXED Card 177 A.4 FIXED Card
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A.5. OPTION Card 179 • DAMP is a
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A.5. OPTION Card 181 A.5.4 Examples
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A.6. SOLVE Card 183 if the voltage
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A.7. Input Deck Specifications 185
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A.9. Examples 187 column contains c
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A.9. Examples 189 fixed num = 1 typ
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A.9. Examples 191 Collector Current
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A.9. Examples 193 title mes.pis mes
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A.9. Examples 195 simulator to use.
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A.9. Examples 197 #Soln #Vctrl Ictr
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Bibliography [1] T.J. Green and W.K
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Bibliography 201 [20] C. Duvvury, R
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Bibliography 203 [42] S.M. Sze, Phy
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Bibliography 205 [63] R. van Overst
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